Datasheet > 暂无类别数据> CY7C1416AV18-200BZC

CY7C1416AV18-200BZC

更新时间： 2024-09-13 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
24页	261K
描述
36-Mbit DDR-II SRAM 2-Word Burst Architecture

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CY7C1416AV18

CY7C1427AV18

CY7C1418AV18

CY7C1420AV18

PRELIMINARY

36-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

• 250-MHz clock for high bandwidth

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and

CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a 1-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read

data is driven on the rising edges of C and C if provided, or on

the rising edge of K and K if C/C are not provided. Each

address location is associated with two 8-bit words in the case

of CY7C1416AV18 and two 9-bit words in the case of

CY7C1427AV18 that burst sequentially into or out of the

device. The burst counter always starts with a “0” internally in

the case of CY7C1416AV18 and CY7C1427AV18. On

CY7C1418AV18 and CY7C1420AV18, the burst counter takes

in the least significant bit of the external address and bursts

two 18-bit words in the case of CY7C1418AV18 and two 36-bit

words in the case of CY7C1420AV18 sequentially into or out

of the device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs D) are tightly matched to the two output echo

clocks CQ/CQ, eliminating the need for separately capturing

data from each individual DDR SRAM in the system design.

Output data clocks (C/C) enable maximum system clocking

and data synchronization flexibility.

• 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,

165 ball (11x15 matrix)

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1416AV18 – 4M x 8

CY7C1427AV18 – 4M x 9

CY7C1418AV18 – 2M x 18

CY7C1420AV18 – 1M x 36

Selection Guide

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

TBD

Shaded areas contain advance information.

Cypress Semiconductor Corporation

Document Number: 38-05616 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 15, 2004

12 3 4 5 6 7...24

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与CY7C1416AV18-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1416AV18-200BZI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-200BZXC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-200BZXI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-250BZC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-250BZI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-250BZXC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-250BZXI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-278BZC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-278BZI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1416AV18-278BZXC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture

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