Datasheet > 存储 > SRAM> CY7C1382D-250BZXC

CY7C1382D-250BZXC

更新时间： 2024-10-11 21:53:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	468K
描述
18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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CY7C1382D-250BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.82	最长访问时间：	2.6 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.07 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	13 mm

CY7C1382D-250BZXC 数据手册

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CY7C1380D

CY7C1382D

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36

and 1,048,576 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

address-pipelining Chip Enable (

), depth-expansion Chip

CE₁

[2]

Enables (CE and

), Burst Control inputs (

CE₃

— 2.6 ns (for 250-MHz device)

ADSC ADSP

), Write Enables (

ADV

, and

BW_X

), and Global Write

and

BWE

— 3.0 ns (for 200-MHz device)

(

). Asynchronous inputs include the Output Enable (

)

— 3.4 ns (for 167-MHz device)

and the ZZ pin.

• Provide high-performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ) or

• User-selectable burst counter supporting Intel^

ADSP

) are active. Subsequent

Pentium interleaved or linear burst sequences

Address Strobe Controller (

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• Separate processor and controller address strobes

• Synchronous self-timed writes

ADV

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

• Single Cycle Chip Deselect

• Offered in JEDEC-standard lead-free 100-pin TQFP,

119-ball BGA and 165-Ball fBGA packages

controlled by the byte write control inputs.

when active

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

causes all bytes to be written.

LOW

The CY7C1380D/CY7C1382D operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

350

300

275

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05543 Rev. *A

Revised October 28, 2004

12 3 4 5 6 7...29

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与CY7C1382D-250BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382D-250BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167AXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167AXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167BGC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1382DV25-167BGXC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
CY7C1382DV25-167BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-167BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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