Datasheet > CY7C1382DV25-200AC

CY7C1382DV25-200AC

更新时间： 2024-11-14 05:56:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	789K
描述
Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1380DV25

CY7C1382DV25

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1380DV25/CY7C1382DV25 SRAM integrates

524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enabl_[e_2](CE₁), depth-

expansion Chip Enables (CE₂and CE₃), Burst Control

inputs (ADSC, ADSP, and ADV), Write Enables (BW_X, and

BWE), and Global Write (GW). Asynchronous inputs include

the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Available speed grades are 250, 225, 200,167, and

133 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

— 4.2 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

causes all bytes to be written.

LOW

• Single Cycle Chip Deselect

The CY7C1380DV25/CY7C1382DV25 operates from a +2.5V

core power supply while all outputs may operate with a +2.5

supply. All inputs and outputs are JEDEC-standard JESD8-5-

compatible.

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Selection Guide

250 MHz

225 MHz

2.8

200 MHz

3.0

167 MHz

3.4

133 MHz

4.2

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.6

350

325

300

275

245

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05546 Rev. **

Revised August 12, 2004

12 3 4 5 6 7...30

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与CY7C1382DV25-200AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382DV25-200AXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-200AXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-200BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1382DV25-200BGXI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
CY7C1382DV25-200BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-200BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-200BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-200BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-225AC	CYPRESS	获取价格	Cache SRAM, 1MX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1382DV25-225BZC	CYPRESS	获取价格	Cache SRAM, 1MX18, 2.8ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165

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