Datasheet > CY7C1382DV25-250BGC

CY7C1382DV25-250BGC

更新时间： 2024-09-26 10:00:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	498K
描述
Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

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CY7C1380DV25

CY7C1382DV25

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

The CY7C1380DV25/CY7C1382DV25 SRAM integrates

512K x 36 and 1M x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE₁), depth-

expansion Chip Enables (CE₂and CE₃^[2]), Burst Control

inputs (ADSC, ADSP, and ADV), Write Enables (BW_X, and

BWE), and Global Write (GW). Asynchronous inputs include

the Output Enable (OE) and the ZZ pin.

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

• Available in JEDEC-standard lead-free 100-pin TQFP,

lead-free and non lead-free 119-ball BGA package and

165-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

causes all bytes to be written.

LOW

The CY7C1380DV25/CY7C1382DV25 operates from a +2.5V

core power supply while all outputs may operate with a +2.5

supply. All inputs and outputs are JEDEC-standard JESD8-5-

compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

350

300

275

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05546 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 27, 2006

12 3 4 5 6 7...29

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与CY7C1382DV25-250BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382DV25-250BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1382DV25-250BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-250BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-250BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV25-250BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382DV33	CYPRESS	获取价格	18-Mbit (512 K Ã 36/1 M Ã 18) Pipelined SRA
CY7C1382DV33-200BZI	CYPRESS	获取价格	18-Mbit (512 K Ã 36/1 M Ã 18) Pipelined SRA
CY7C1382F	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-167AXI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 20 X 14 MM, 1.4 MM HEIGHT, LEAD FREE, PLASTIC, MS
CY7C1382F-167BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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