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CY7C1362B-225BZI PDF预览

CY7C1362B-225BZI

更新时间： 2024-09-27 22:28:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
34页 859K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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中文翻译

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CY7C1362B-225BZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.20 MM HEIGHT, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.81
最长访问时间：2.8 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：225 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.03 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

CY7C1362B-225BZI 数据手册

 浏览型号CY7C1362B-225BZI的Datasheet PDF文件第2页浏览型号CY7C1362B-225BZI的Datasheet PDF文件第3页浏览型号CY7C1362B-225BZI的Datasheet PDF文件第4页浏览型号CY7C1362B-225BZI的Datasheet PDF文件第5页浏览型号CY7C1362B-225BZI的Datasheet PDF文件第6页浏览型号CY7C1362B-225BZI的Datasheet PDF文件第7页 
CY7C1360B  
CY7C1362B  
9-Mbit(256Kx36/512Kx18)PipelinedSRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 225 MHz  
• Available speed grades are 225, 200 and 166 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
• 2.5V/3.3V I/O operation  
• Fast clock-to-output times  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36  
and 524,288 x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (  
), depth-expansion Chip  
CE1  
[2]  
Enables (CE and  
), Burst Control inputs (  
,
,
CE3  
2
ADSC ADSP  
), Write Enables (  
ADV  
, and  
BWX  
), and Global Write  
and  
BWE  
(
). Asynchronous inputs include the Output Enable (  
)
OE  
GW  
and the ZZ pin.  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor ( ) or  
• Provide high-performance 3-1-1-1 access rate  
ADSP  
) are active. Subsequent  
Address Strobe Controller (  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• User-selectable burst counter supporting Intel  
Pentium® interleaved or linear burst sequences  
ADV  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
• Single Cycle Chip Deselect  
controlled by the Byte Write control inputs.  
when active  
GW  
causes all bytes to be written.  
LOW  
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA  
and 165-Ball fBGA packages  
The CY7C1360B/CY7C1362B operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
• TQFP Available with 3-Chip Enable and 2-Chip Enable  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
Selection Guide  
225 MHz  
200 MHz  
3.0  
166 MHz  
3.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
2.8  
250  
30  
220  
30  
180  
30  
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05291 Rev. *C  
Revised April 9, 2004  
1234567...34

中文翻译

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CY7C1362B-250BGC CYPRESS

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CY7C1362C CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AJXC CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AJXC INFINEON

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 		Synchronous SRAM
CY7C1362C-166AJXCT ROCHESTER

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 		Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,
CY7C1362C-166AJXI CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AXC CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AXCT ROCHESTER

获取价格

 		Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,

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