Datasheet > CY7C1362B-250BZC

CY7C1362B-250BZC

更新时间： 2024-09-28 21:14:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
31页	805K
描述
Cache SRAM, 512KX18, 3.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1362B-250BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.81
最长访问时间：	3.4 ns	其他特性：	PIPELINE ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1362B-250BZC 数据手册

CY7C1360B

CY7C1362B

PRELIMINARY

256K x 36/512K x 18 Pipelined SRAM

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 2.6 ns (250 MHz

Features

• Supports bus operation up to 250 MHz

— Available speed grades are 250, 200, and 166 MHz

device).

• Fully registered inputs and outputs for pipelined

operation

• Single 3.3V power supply

• Supports 3.3V and 2.5V I/Os

• Fast clock-to-output times

— 2.6ns (for 250-MHz device)

The CY7C1360B and CY7C1362B support either the inter-

leaved burst sequence used by the Intel Pentium processor or

a linear burst sequence used by processors such as the

PowerPC™. The burst sequence is selected through the

MODE pin (Pin 31 and ball R3 for the TQFP and BGA

packages, respectively.) Accesses can be initiated by

asserting either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC) at clock rise. Address

advancement through the burst sequence is controlled by the

ADV input. A 2-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.

— 3.0ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball

fBGA

Byte write operations are qualified with the Byte Write Select

(BW_a,b,c,dfor 1360B and BW_a,bfor 1362B) inputs. A Global

Write Enable (GW) overrides all byte write inputs and writes

data to all four bytes. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a read cycle when emerging from a deselected

state.

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1360B and CY7C1362B are 3.3V, 256K x 36 and

512K x 18 synchronous-pipelined cache SRAM, respectively.

CLK

Logic Block Diagram

Data-In REG.

ADV

CONTROL

and WRITE

LOGIC

256Kx36/

512Kx18

1360B

1362B

DQP

MEMORY

ARRAY

[17:0]

[18:0]

BWE

a,b

a,b,c,d

DQP

a,b,c,d

a,b

MODE

ADSP

ADSC

a,b,c,d

a,b

Selection Table

CY7C1360B-250

CY7C1362B-250

CY7C1360B-200

CY7C1362B-200

CY7C1360B-166

CY7C1362B-166

Unit

Maximum Access Time

2.6

250

3.0

220

3.5

180

Maximum Operating Current

Commercial

Maximum CMOS Standby Current Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05291 Rev. *A

Revised August 15, 2002

12 3 4 5 6 7...31

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与CY7C1362B-250BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1362C	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AJXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AJXC	INFINEON	获取价格	Synchronous SRAM
CY7C1362C-166AJXCT	ROCHESTER	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,
CY7C1362C-166AJXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166AXCT	ROCHESTER	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,
CY7C1362C-166AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BGCT	CYPRESS	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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