Datasheet > 暂无类别数据> CY7C1354DV25-250AXI

CY7C1354DV25-250AXI

更新时间： 2024-11-20 06:51:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	847K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

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CY7C1354DV25, CY7C1356DV25

9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

The CY7C1354DV25 and CY7C1356DV25 are 2.5V, 256K x 36

and 512K x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back to back read and write operations

with no wait states. The CY7C1354DV25 and CY7C1356DV25

are equipped with the advanced (NoBL) logic required to enable

consecutive read and write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent write and

read transitions. The CY7C1354DV25 and CY7C1356DV25 are

pin compatible with and functionally equivalent to ZBT devices.

■

Pin compatible with and functionally equivalent to ZBT™

Supports 250 MHz bus operations with zero wait states

Available speed grades are 250, 200, and 166 MHz

Internally self timed output buffer control to eliminate the need

to use asynchronous OE

■

Fully registered (inputs and outputs) for pipelined operation

Byte Write capability

Single 2.5V power supply (V_DD

Fast clock-to-output times

)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

❐

2.8 ns (for 250 MHz device)

■

Clock Enable (CEN) pin to suspend operation

Synchronous self timed writes

Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1354DV25 and BW_a–BW_bfor

CY7C1356DV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self timed write circuitry.

Available in Pb-free 100-pin TQFP package, Pb-free and non

Pb-free 119-ball BGA package, and 165-ball FBGA package

■

IEEE 1149.1 JTAG compatible boundary scan

Burst capability–linear or interleaved burst order

“ZZ” Sleep mode and Stop Clock options

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide easy bank selection

and output tri-state control. To avoid bus contention, the output

drivers are synchronously tri-stated during the data portion of a

write sequence. For best practices recommendations, please

refer to the Cypress application note System Design Guidelines

on www.cypress.com.

Selection Guide

Description

250 MHz

2.8

200 MHz

3.2

166 MHz

3.5

Unit

Maximum Access Time

Maximum Operating Current

250

220

180

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document #: 001-48974 Rev. *A

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 31, 2009

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与CY7C1354DV25-250AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354DV25-250BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354V25	ETC	获取价格	Memory
CY7C1354V25-100AC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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