Datasheet > 存储 > SRAM> CY7C1315BV18-278BZXI

CY7C1315BV18-278BZXI

更新时间： 2024-11-16 05:19:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
28页	501K
描述
18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture

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CY7C1315BV18-278BZXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.77
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	278 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.25 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.53 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

CY7C1315BV18-278BZXI 数据手册

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CY7C1311BV18

CY7C1911BV18

CY7C1313BV18

CY7C1315BV18

18-Mbit QDR™-II SRAM 4-Word

Burst Architecture

Features

Functional Description

• Separate Independent Read and Write data ports

— Supports concurrent transactions

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and

CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 8-bit words (CY7C1311BV18) or 9-bit

words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or

36-bit words (CY7C1315BV18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K and

K and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

• 300-MHz clock for high bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 600 MHz) at 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x 8, x 9, x 18, and x 36 configurations

• Full data coherency providing most current data

• Core V_DD= 1.8 (±0.1V); I/O V_DDQ= 1.4V to V_DD

• Available in 165-ballFBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non-lead free packages

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1311BV18 – 2M x 8

CY7C1911BV18 – 2M x 9

CY7C1313BV18 – 1M x 18

CY7C1315BV18 – 512K x 36

Selection Guide

300 MHz

300

278 MHz

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

278

530

550

500

450

400

Cypress Semiconductor Corporation

Document Number: 38-05620 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 27, 2006

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与CY7C1315BV18-278BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1315BV18-300BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-300BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-300BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315BV18-300BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18-167BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18-167BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18-167BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18-167BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1315CV18-200BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II SRAM 4-Word Burst Architectur

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