Datasheet > 存储 > SRAM> CY7C1315JV18-250BZXI

CY7C1315JV18-250BZXI

更新时间： 2024-11-16 11:47:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	669K
描述
18-Mbit QDR II SRAM 4-Word Burst Architecture

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技术参数
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CY7C1315JV18-250BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, FPBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.8	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	QDR SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.325 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.83 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

CY7C1315JV18-250BZXI 数据手册

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CY7C1311JV18/CY7C1911JV18

CY7C1313JV18/CY7C1315JV18

18-Mbit QDR^®II SRAM 4-Word

Burst Architecture

Features

Configurations

■

Separate Independent Read and Write Data Ports

Supports concurrent transactions

CY7C1311JV18 – 2M x 8

CY7C1911JV18 – 2M x 9

CY7C1313JV18 – 1M x 18

CY7C1315JV18 – 512K x 36

❐

■

300 MHz Clock for High Bandwidth

4-word Burst for reducing Address Bus Frequency

DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 600 MHz) at 300 MHz

Functional Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and

CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR II architecture. QDR II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR II architecture has

separate data inputs and data outputs to eliminate the need to

‘turnaround’ the data bus required with common IO devices.

Access to each port is accomplished through a common address

bus. Addresses for read and write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

QDR II read and write ports are completely independent of one

another. In order to maximize data throughput, both read and

write ports are provided with DDR interfaces. Each address

location is associated with four 8-bit words (CY7C1311JV18) or

9-bit words (CY7C1911JV18) or 18-bit words (CY7C1313JV18)

or 36-bit words (CY7C1315JV18) that burst sequentially into or

out of the device. Because data is transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

■

Two Input Clocks (K and K) for Precise DDR Timing

❐

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

Single Multiplexed Address Input Bus latches Address Inputs

for both Read and Write Ports

■

Separate Port Selects for Depth Expansion

Synchronous Internally Self-timed Writes

QDR^®IIOperateswith1.5CycleReadLatencywhentheDelay

Lock Loop (DLL) is enabled

■

Operates like a QDR I device with 1 Cycle Read Latency in

DLL Off Mode

■

Available in x8, x9, x18, and x36 configurations

Full Data Coherency, providing most current Data

Core V_DD= 1.8 (±0.1V); IO V_DDQ= 1.4V to V_DD

Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

Variable Drive HSTL Output Buffers

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

JTAG 1149.1 Compatible Test Access Port

Delay Lock Loop (DLL) for Accurate Data Placement

Selection Guide

Description

300 MHz

300

250 MHz

250

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

730

665

735

675

x18

x36

790

705

895

830

Cypress Semiconductor Corporation

Document Number: 001-12562 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised August 04, 2009

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与CY7C1315JV18-250BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1315JV18-300BZC	CYPRESS	获取价格	18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1315JV18-300BZI	CYPRESS	获取价格	18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1315JV18-300BZXC	CYPRESS	获取价格	18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1315JV18-300BZXI	CYPRESS	获取价格	18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1315KV18	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZCT	CYPRESS	获取价格	Standard SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-16
CY7C1315KV18-250BZI	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZI_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite

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