Datasheet > CY7C1268XV18-633BZXC

CY7C1268XV18-633BZXC

更新时间： 2024-03-03 10:11:23

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
29页	880K
描述
Synchronous SRAM

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CY7C1268XV18

CY7C1270XV18

36-Mbit DDR II+ Xtreme SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency)

36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ 36-Mbit density (2 M × 18, 1 M × 36)

■ 633 MHz clock for high bandwidth

With Read Cycle Latency of 2.5 cycles:

CY7C1268XV18 – 2 M × 18

CY7C1270XV18 – 1 M × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

1266 MHz) at 633 MHz

Functional Description

The CY7C1268XV18, and CY7C1270XV18 are 1.8 V

synchronous pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C1268XV18), or 36-bit words (CY7C1270XV18) that burst

sequentially into or out of the device.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ DDR II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen

DOFF is asserted LOW

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 × 15 × 1.4 mm)

For a complete list of related documentation, click here.

■ Offered in Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

633 MHz

633

600 MHz Unit

600

910

MHz

Maximum operating current

× 18

× 36

965

1230

1165

Cypress Semiconductor Corporation

Document Number: 001-70329 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 15, 2017

123 4 5 6 7...29

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与CY7C1268XV18-633BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1270KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270KV18-400BZC	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270KV18-400BZXC	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1270KV18-400BZXI	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270KV18-400BZXI	INFINEON	获取价格	DDR-II+ CIO
CY7C1270KV18-550BZC	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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