CY7C1268XV18
CY7C1270XV18
Pin Definitions (continued)
Pin Name
TDO
I/O
Output
Input
Input
Input
N/A
Pin Description
Test data out (TDO) pin for JTAG.
Test clock (TCK) pin for JTAG.
Test data in (TDI) pin for JTAG.
Test mode select (TMS) pin for JTAG.
TCK
TDI
TMS
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
VREF
Input
Input
Input
Input-
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
Reference measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
When read access is deselected, the CY7C1268XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the negative input clock (K). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.
Functional Overview
The CY7C1268XV18, and CY7C1270XV18 are synchronous
pipelined Burst SRAMs equipped with a DDR interface, which
operates with a read latency of two and half cycles when DOFF
pin is tied HIGH. When DOFF pin is set LOW or connected to
VSS the device behaves in DDR I mode with a read latency of
one clock cycle.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the negative input clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS[X:0]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1268XV18 is described in the following sections. The
same basic descriptions apply to CY7C1270XV18.
Read Operations
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
The CY7C1268XV18 is organized internally as two arrays of
1 M × 18. Accesses are completed in a burst of 2 sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q[17:0] using K as the output timing reference.
On the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
Byte Write Operations
Byte write operations are supported by the CY7C1268XV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Document Number: 001-70329 Rev. *F
Page 6 of 28
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