Datasheet > 暂无类别数据> CY7C1270KV18-400BZXI

CY7C1270KV18-400BZXI

更新时间： 2024-01-14 19:41:38

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	898K
描述
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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CY7C1270KV18-400BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.53
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	400 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	37748736 bit
内存集成电路类型：	DDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.31 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.69 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm

CY7C1270KV18-400BZXI 数据手册

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CY7C1266KV18, CY7C1277KV18

CY7C1268KV18, CY7C1270KV18

36-Mbit DDR II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)

■ 550 MHz clock for high bandwidth

With Read Cycle Latency of 2.5 Cycles:

CY7C1266KV18 – 4 M × 8

CY7C1277KV18 – 4 M × 9

■ 2-word burst for reducing address bus frequency

CY7C1268KV18 – 2 M × 18

CY7C1270KV18 – 1 M × 36

■ Double data rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

Functional Description

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and

CY7C1270KV18 are 1.8 V synchronous pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1266KV18), 9-bit words (CY7C1277KV18), 18-bit

words (CY7C1268KV18), or 36-bit words (CY7C1270KV18) that

burst sequentially into or out of the device.

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Phase-locked loop (PLL) for accurate data placement

Table 1. Selection Guide

Description

Maximum operating frequency

550 MHz

500 MHz

500

450 MHz

450

400 MHz

400

Unit

MHz

550

690

700

890

Maximum operating current

× 8

× 9

640

590

540

640

590

540

× 18

× 36

650

600

550

830

760

690

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-57835 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 24, 2011

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与CY7C1270KV18-400BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1270KV18-550BZC	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1270V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-333BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-333BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-333BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1270V18-333BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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