Datasheet > CY7C1265XV18-633BZXC

CY7C1265XV18-633BZXC

更新时间： 2024-04-09 18:58:35

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
31页	1390K
描述
Synchronous SRAM

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中文翻译

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数据手册

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CY7C1265XV18-633BZXC 数据手册

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CY7C1263XV18

CY7C1265XV18

Logic Block Diagram – CY7C1263XV18

[17:0]

Write Write Write Write

Address

Reg

(18:0)

Address

(18:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

WPS

BWS

[17:0]

[1:0]

QVLD

Logic Block Diagram – CY7C1265XV18

[35:0]

Write Write Write Write

Address

Reg

(17:0)

Address

(17:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

144

REF

Reg.

Control

Logic

WPS

BWS

[35:0]

[3:0]

QVLD

Document Number: 001-70328 Rev. *F

Page 2 of 30

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与CY7C1265XV18-633BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1266KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1266V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)