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CY7C1265XV18-633BZXC PDF预览

CY7C1265XV18-633BZXC

更新时间: 2024-04-09 18:58:35
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英飞凌 - INFINEON 静态存储器
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31页 1390K
描述
Synchronous SRAM

CY7C1265XV18-633BZXC 数据手册

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CY7C1263XV18  
CY7C1265XV18  
Pin Definitions (continued)  
Pin Name  
TDO  
I/O  
Output  
Input  
Input  
Input  
N/A  
Pin Description  
TDO Pin for JTAG  
TCK Pin for JTAG  
TDI Pin for JTAG  
TMS Pin for JTAG  
TCK  
TDI  
TMS  
NC  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
NC/72M  
NC/144M  
NC/288M  
VREF  
N/A  
N/A  
N/A  
Input-  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC  
Reference measurement points.  
VDD  
VSS  
Power Supply Power Supply Inputs to the Core of the Device  
Ground  
Ground for the Device  
VDDQ  
Power Supply Power Supply Inputs for the Outputs of the Device  
RPS active at the rising edge of the positive input clock (K). The  
address presented to the address inputs is stored in the read  
address register. Following the next two K clock rise, the  
corresponding lowest order 18-bit word of data is driven onto the  
Q[17:0] using K as the output timing reference. On the  
subsequent rising edge of K, the next 18-bit data word is driven  
onto the Q[17:0]. This process continues until all four 18-bit data  
words have been driven out onto Q[17:0]. The requested data is  
valid 0.45 ns from the rising edge of the input clock (K or K). To  
maintain the internal logic, each read access must be allowed to  
complete. Each read access consists of four 18-bit data words  
and takes two clock cycles to complete. Therefore, read  
accesses to the device can not be initiated on two consecutive  
K clock rises. The internal logic of the device ignores the second  
read request. Read accesses can be initiated on every other K  
clock rise. Doing so pipelines the data flow such that data is  
transferred out of the device on every rising edge of the input  
clocks (K and K).  
Functional Overview  
The CY7C1263XV18 and CY7C1265XV18 are synchronous  
pipelined Burst SRAMs equipped with a read port and a write  
port. The read port is dedicated to read operations and the write  
port is dedicated to write operations. Data flows into the SRAM  
through the write port and flows out through the read port. These  
devices multiplex the address inputs to minimize the number of  
address pins required. By having separate read and write ports,  
the QDR II+ Xtreme completely eliminates the need to  
“turnaround” the data bus and avoids any possible data  
contention, thereby simplifying system design. Each access  
consists of four 18-bit data transfers in the case of  
CY7C1263XV18, and four 36-bit data transfers in the case of  
CY7C1265XV18, in two clock cycles.  
These devices operate with a read latency of two and half cycles  
when DOFF pin is tied HIGH. When DOFF pin is set LOW or  
connected to VSS then device behaves in QDR I mode with a  
read latency of one clock cycle.  
When the read port is deselected, the CY7C1263XV18 first  
completes the pending read transactions. Synchronous internal  
circuitry automatically tristates the outputs following the next  
rising edge of the negative input clock (K). This enables for a  
seamless transition between devices without the insertion of wait  
states in a depth expanded memory.  
Accesses for both ports are initiated on the positive input clock  
(K). All synchronous input and output timing are referenced from  
the rising edge of the input clocks (K and K).  
All synchronous data inputs (D[x:0]) pass through input registers  
controlled by the input clocks (K and K). All synchronous data  
outputs (Q[x:0]) outputs pass through output registers controlled  
by the rising edge of the input clocks (K and K) as well.  
Write Operations  
Write operations are initiated by asserting WPS active at the  
rising edge of the positive input clock (K). On the following K  
clock rise the data presented to D[17:0] is latched and stored into  
the lower 18-bit write data register, provided BWS[1:0] are both  
asserted active. On the subsequent rising edge of the negative  
input clock (K) the information presented to D[17:0] is also stored  
into the write data register, provided BWS[1:0] are both asserted  
active. This process continues for one more cycle until four 18-bit  
words (a total of 72 bits) of data are stored in the SRAM. The  
72 bits of data are then written into the memory array at the  
specified location. Therefore, write accesses to the device can  
not be initiated on two consecutive K clock rises. The internal  
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass  
through input registers controlled by the rising edge of the input  
clocks (K and K).  
CY7C1263XV18 is described in the following sections. The  
same basic descriptions apply to CY7C1265XV18.  
Read Operations  
The CY7C1263XV18 is organized internally as four arrays of  
512 K × 18. Accesses are completed in a burst of four sequential  
18-bit data words. Read operations are initiated by asserting  
Document Number: 001-70328 Rev. *F  
Page 6 of 30  

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