CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 550 MHz clock for high bandwidth
With Read Cycle Latency of 2.5 Cycles:
CY7C1266KV18 – 4 M × 8
CY7C1277KV18 – 4 M × 9
■ 2-word burst for reducing address bus frequency
CY7C1268KV18 – 2 M × 18
CY7C1270KV18 – 1 M × 36
■ Double data rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
Functional Description
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
The CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and
CY7C1270KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1266KV18), 9-bit words (CY7C1277KV18), 18-bit
words (CY7C1268KV18), or 36-bit words (CY7C1270KV18) that
burst sequentially into or out of the device.
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
DOFF is asserted LOW
[1]
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Phase-locked loop (PLL) for accurate data placement
Table 1. Selection Guide
Description
Maximum operating frequency
550 MHz
500 MHz
500
450 MHz
450
400 MHz
400
Unit
MHz
mA
550
690
690
700
890
Maximum operating current
× 8
× 9
640
590
540
640
590
540
× 18
× 36
650
600
550
830
760
690
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-57835 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 24, 2011
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