是否Rohs认证: | 符合 | 生命周期: | Obsolete |
零件包装代码: | BGA | 包装说明: | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
针数: | 165 | Reach Compliance Code: | unknown |
ECCN代码: | 3A991.B.2.A | HTS代码: | 8542.32.00.41 |
风险等级: | 5.78 | 最长访问时间: | 0.45 ns |
其他特性: | PIPELINED ARCHITECTURE | 最大时钟频率 (fCLK): | 400 MHz |
I/O 类型: | COMMON | JESD-30 代码: | R-PBGA-B165 |
JESD-609代码: | e1 | 长度: | 17 mm |
内存密度: | 37748736 bit | 内存集成电路类型: | DDR SRAM |
内存宽度: | 18 | 湿度敏感等级: | 3 |
功能数量: | 1 | 端子数量: | 165 |
字数: | 2097152 words | 字数代码: | 2000000 |
工作模式: | SYNCHRONOUS | 最高工作温度: | 70 °C |
最低工作温度: | 组织: | 2MX18 | |
输出特性: | 3-STATE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LBGA | 封装等效代码: | BGA165,11X15,40 |
封装形状: | RECTANGULAR | 封装形式: | GRID ARRAY, LOW PROFILE |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | 260 |
电源: | 1.5/1.8,1.8 V | 认证状态: | Not Qualified |
座面最大高度: | 1.4 mm | 最大待机电流: | 0.34 A |
最小待机电流: | 1.7 V | 子类别: | SRAMs |
最大压摆率: | 1.28 mA | 最大供电电压 (Vsup): | 1.9 V |
最小供电电压 (Vsup): | 1.7 V | 标称供电电压 (Vsup): | 1.8 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子面层: | Tin/Silver/Copper (Sn/Ag/Cu) |
端子形式: | BALL | 端子节距: | 1 mm |
端子位置: | BOTTOM | 处于峰值回流温度下的最长时间: | 20 |
宽度: | 15 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CY7C1268V18-400BZXI | CYPRESS |
获取价格 |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1268XV18 | CYPRESS |
获取价格 |
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1268XV18-600BZXC | CYPRESS |
获取价格 |
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1268XV18-633BZXC | CYPRESS |
获取价格 |
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1268XV18-633BZXC | INFINEON |
获取价格 |
Synchronous SRAM | |
CY7C1270KV18 | CYPRESS |
获取价格 |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1270KV18-400BZC | CYPRESS |
获取价格 |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1270KV18-400BZXC | CYPRESS |
获取价格 |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1270KV18-400BZXC | INFINEON |
获取价格 |
DDR-II+ CIO | |
CY7C1270KV18-400BZXI | CYPRESS |
获取价格 |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |