Datasheet > CY7C1265XV18-633BZXC

CY7C1265XV18-633BZXC

更新时间： 2024-04-09 18:58:35

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
31页	1390K
描述
Synchronous SRAM

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CY7C1263XV18

CY7C1265XV18

36-Mbit QDR^®II+ Xtreme SRAM Four-Word

Burst Architecture (2.5 Cycle Read Latency)

36-Mbit QDR^®II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ Separate Independent Read and Write Data Ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 cycles:

CY7C1263XV18 – 2 M × 18

■ 633 MHz Clock for High Bandwidth

CY7C1265XV18 – 1 M × 36

■ Four-word Burst for Reducing Address Bus Frequency

Functional Description

■ Double Data Rate (DDR) Interfaces on both Read and Write

The CY7C1263XV18, and CY7C1265XV18 are 1.8 V

Synchronous Pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ Xtreme read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CY7C1263XV18), or 36-bit words (CY7C1265XV18) that

burst sequentially into or out of the device. Because data is

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turnarounds”.

Ports (data transferred at 1266 MHz) at 633 MHz

■ Available in 2.5 Clock Cycle Latency

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Data Valid Pin (QVLD) to indicate Valid Data on the Output

■ Single Multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

■ Separate Port selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR^®II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ Operates similar to QDR I Device with one Cycle Read Latency

when DOFF is asserted LOW

■ Available in × 18 and × 36 Configurations

■ Full Data Coherency, providing Most Current Data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL Inputs and Variable Drive HSTL Output Buffers

■ Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)

■ Offered in Pb-free Packages

For a complete list of related documentation, click here.

■ JTAG 1149.1 compatible Test Access Port

■ Phase-Locked Loop (PLL) for Accurate Data Placement

Selection Guide

Description

Maximum Operating Frequency

633 MHz

633

600 MHz Unit

600

1100

1570

MHz

Maximum Operating Current

× 18

× 36

1165

1660

Cypress Semiconductor Corporation

Document Number: 001-70328 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 3, 2018

123 4 5 6 7...31

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与CY7C1265XV18-633BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1266KV18	CYPRESS	获取价格	36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1266V18	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZXC	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1266V18-333BZXI	CYPRESS	获取价格	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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