Datasheet > CY7C11651KV18

CY7C11651KV18

更新时间： 2024-11-07 09:43:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	874K
描述
18-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C11651KV18 数据手册

CY7C11611KV18, CY7C11761KV18

CY7C11631KV18, CY7C11651KV18

18-Mbit QDR^®II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

18-Mbit QDR^®II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ Separate independent read and write data ports

❐ Supports concurrent transactions

The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18,

and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR II+ architecture. Similar to QDR II archi-

tecture, QDR II+ architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

■ 550 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

and the write port has dedicated data inputs to support write

operations. QDR II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn around”

the data bus that exists with common I/O devices. Each port is

accessed through a common address bus. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Accesses to the QDR II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 8-bit

words (CY7C11611KV18), 9-bit words (CY7C11761KV18),

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

18-bit

words

(CY7C11631KV18),

36-bit

words

■ Separate port selects for depth expansion

■ Synchronous internally self timed writes

(CY7C11651KV18) that burst sequentially into or out of the

device. Because data is transferred into and out of the device on

every rising edge of both input clocks (K and K), memory

bandwidth is maximized while simplifying system design by

eliminating bus “turn arounds”.

■ QDR^®II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

[1]

■ Core V_DD= 1.8V± 0.1V; I/O V_DDQ= 1.4V to V_DD

❐ Supports both 1.5V and 1.8V I/O supply

These devices are down bonded from the 65 nm 72M

QDRII+/DDRII+ devices and hence have the same I_DD/I_SB1

values and JTAG ID code as the equivalent 72M device options.

For details refer to the application note AN53189, 65 nm

Technology Interim QDRII+/DDRII+ SRAM Device Family

Description.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

Table 1. Selection Guide

550 500 450 400

■ Phase Locked Loop (PLL) for accurate data placement

Description

Unit

MHz MHz MHz MHz

Configurations

Maximum Operating

Frequency

550 500 450 400 MHz

With Read cycle latency of 2.5 cycles:

CY7C11611KV18 – 2M x 8

Maximum Operating

Current

x8 900 830 760 690 mA

x9 900 830 760 690

x18 920 850 780 710

x36 1310 1210 1100 1000

CY7C11761KV18 – 2M x 9

CY7C11631KV18 – 1M x 18

CY7C11651KV18 – 512K x 36

Cypress Semiconductor Corporation

Document Number: 001-53197 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 31, 2011

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与CY7C11651KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C11651KV18-400BZXC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165KV18	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165KV18-400BZC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165KV18-400BZXC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165KV18-400BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1165KV18-550BZC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165KV18-550BZC	INFINEON	获取价格	Synchronous SRAM
CY7C1165KV18-550BZXC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1165V18	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-300BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu

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