Datasheet > 存储 > SRAM> CY7C1165V18-300BZC

CY7C1165V18-300BZC

更新时间： 2024-11-07 04:53:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
29页	1175K
描述
18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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技术参数
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CY7C1165V18-300BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.91
Is Samacsys：	N	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	300 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	QDR SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.25 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.85 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1165V18-300BZC 数据手册

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CY7C1161V18

CY7C1176V18

CY7C1163V18

CY7C1165V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ Separate independent read and write data ports

❐ Supports concurrent transactions

The CY7C1161V18, CY7C1176V18, CY7C1163V18, and

CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

■ 300 MHz to 400 MHz clock for high bandwidth

■ 4-word burst to reduce address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 800 MHz) at 400 MHz

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to turn around the

data bus that is required with common IO devices. Each port can

be accessed through a common address bus. Addresses for

read and write addresses are latched onto alternate rising edges

of the input (K) clock. Accesses to the QDR-II+ read and write

ports are completely independent of one another. In order to

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words

(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K, memory bandwidth is maximized while simpli-

fying system design by eliminating bus turnarounds.

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

Depth expansion is accomplished with port selects for each port.

Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the or K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With cycle read latency of 2.5 cycles:

CY7C1161V18 – 2M x 8

CY7C1176V18 – 2M x 9

CY7C1163V18 – 1M x 18

CY7C1165V18 – 512K x 36

Selection Guide

400 MHz

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

400

1080

1020

920

850

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06582 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2007

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与CY7C1165V18-300BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1165V18-300BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-300BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-300BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-333BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-333BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-333BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-333BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1165V18-375BZC	CYPRESS	获取价格	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
CY7C1165V18-375BZXC	CYPRESS	获取价格	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1165V18-375BZXI	CYPRESS	获取价格	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F

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