Datasheet > CY7C1150KV18-400BZXI

CY7C1150KV18-400BZXI

更新时间： 2024-04-09 18:40:59

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CY7C1150KV18-400BZXI 数据手册

CY7C1148KV18/CY7C1150KV18

Document History Page (continued)

Document Title: CY7C1148KV18/CY7C1150KV18, 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read

Latency)

Document Number: 001-58912

Orig. of

Change

Submission

Date

Rev.

ECN

Description of Change

4653482

PRIT

02/06/2015 Updated Ordering Information (Updated part numbers).

Completing Sunset Review.

5092859

PRIT

01/19/2016 Updated Package Diagram:

spec 51-85180 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

6013687 AESATP12 01/04/2018 Updated logo and copyright.

Document Number: 001-58912 Rev. *I

Page 28 of 29

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型号	品牌	获取价格	描述	数据表
CY7C1150KV18-450BZC	CYPRESS	获取价格	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-300BZC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1150V18-300BZXC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-300BZXI	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)