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CY7C1150KV18-400BZXI PDF预览

CY7C1150KV18-400BZXI

更新时间: 2024-04-09 18:40:59
品牌 Logo 应用领域
英飞凌 - INFINEON 双倍数据速率
页数 文件大小 规格书
29页 770K
描述
DDR-II+ CIO

CY7C1150KV18-400BZXI 数据手册

 浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第23页浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第24页浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第25页浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第26页浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第28页浏览型号CY7C1150KV18-400BZXI的Datasheet PDF文件第29页 
CY7C1148KV18/CY7C1150KV18  
Document History Page  
Document Title: CY7C1148KV18/CY7C1150KV18, 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read  
Latency)  
Document Number: 001-58912  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN  
Description of Change  
**  
2864051  
2894043  
VKN  
01/22/2010 New data sheet.  
*A  
AJU /  
PYRS  
03/17/10  
Updated Ordering Information:  
Removed all inactive parts.  
*B  
3083280  
NJY  
11/10/2010 Changed status from Preliminary to Final.  
Updated Ordering Information:  
Updated part numbers.  
Added Ordering Code Definitions.  
Added Acronyms and Units of Measure.  
*C  
*D  
3181270  
3880082  
SHTC  
PRIT  
02/24/2011 Updated Ordering Information:  
Updated part numbers.  
01/22/2013 Updated Features (Removed CY7C1146KV18, CY7C1157KV18 related  
information).  
Updated Configurations (Removed CY7C1146KV18, CY7C1157KV18 related  
information).  
Updated Functional Description (Removed CY7C1146KV18, CY7C1157KV18  
related information).  
Updated Selection Guide (Removed CY7C1146KV18, CY7C1157KV18  
related information, removed 375 MHz, 333 MHz frequencies related  
information).  
Removed Logic Block Diagram – CY7C1146KV18.  
Removed Logic Block Diagram – CY7C1157KV18.  
Updated Pin Configurations (Removed CY7C1146KV18, CY7C1157KV18  
related information).  
Updated Pin Definitions (Removed CY7C1146KV18, CY7C1157KV18 related  
information).  
Updated Functional Overview (Removed CY7C1146KV18, CY7C1157KV18  
related information).  
Updated Truth Table (Removed CY7C1146KV18, CY7C1157KV18 related  
information).  
Updated Write Cycle Descriptions (Removed CY7C1146KV18 related  
information).  
Removed Write Cycle Descriptions (Corresponding to CY7C1157KV18).  
Updated Identification Register Definitions (Removed CY7C1146KV18,  
CY7C1157KV18 related information).  
Updated Electrical Characteristics (Removed CY7C1146KV18,  
CY7C1157KV18 related information, removed 375 MHz, 333 MHz frequencies  
related information).  
Updated Switching Characteristics (Removed 375 MHz, 333 MHz frequencies  
related information).  
Updated Package Diagram:  
spec 51-85180 – Changed revision from *C to *F.  
*E  
*F  
4375012  
4578255  
PRIT  
PRIT  
05/09/2014 Updated Application Example:  
Updated Figure 2.  
Updated Thermal Resistance:  
Updated values of JA parameter.  
Included JB parameter and its details.  
Updated to new template.  
11/25/2014 Updated Functional Description:  
Added “For a complete list of related documentation, click here.” at the end.  
Updated Ordering Information:  
Updated part numbers.  
Document Number: 001-58912 Rev. *I  
Page 27 of 29  

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18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
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CY7C1150V18-333BZXC CYPRESS

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18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXI CYPRESS

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18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZC CYPRESS

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