020CY7C10
CY7C1020
32K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Features
• 5.0V operation (± 10%)
• High speed
— tAA = 10 ns
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
• Low active power
— 825 mW (max., 10 ns, “L” version)
• Very Low standby power
— 550 µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1020 is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
The CY7C1020 is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
NC
1
A
0
43
42
41
40
39
38
A
A
14
13
12
2
3
4
5
6
1
A
A
2
A
A
A
OE
6
11
A
BHE
BLE
I/O
I/O
I/O
5
CE
I/O
I/O
I/O
A
A
A
4
3
2
1
32K x 16
RAM Array
I/O – I/O
1
8
7
1
16
37
36
35
34
33
8
2
3
15
14
13
I/O – I/O
9
9
16
A
A
10
11
12
13
I/O
V
I/O
4
0
V
SS
CC
V
V
SS
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
31
30
29
28
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
18
NC
27
26
25
A
A
10
3
BHE
19
20
21
22
A
4
A
9
8
7
WE
CE
OE
A
A
5
A
6
A
24
23
1020-2
NC
NC
BLE
1020-1
Selection Guide
7C1020-10
7C1020-12
7C1020-15
7C1020-20
Maximum Access Time (ns)
10
180
150
3
12
170
140
3
15
160
130
3
20
160
130
3
Maximum Operating Current (mA)
L
L
Maximum CMOS Standby Current (mA)
0.1
0.1
0.1
0.1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05058 Rev. **
Revised August 31, 2001
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