5秒后页面跳转
CY7C1019CV33_11 PDF预览

CY7C1019CV33_11

更新时间: 2022-10-24 12:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 442K
描述
1-Mbit (128 K × 8) Static RAM Center Power/Ground Pinout

CY7C1019CV33_11 数据手册

 浏览型号CY7C1019CV33_11的Datasheet PDF文件第2页浏览型号CY7C1019CV33_11的Datasheet PDF文件第3页浏览型号CY7C1019CV33_11的Datasheet PDF文件第4页浏览型号CY7C1019CV33_11的Datasheet PDF文件第5页浏览型号CY7C1019CV33_11的Datasheet PDF文件第6页浏览型号CY7C1019CV33_11的Datasheet PDF文件第7页 
CY7C1019CV33  
1-Mbit (128 K × 8) Static RAM  
1-Mbit (128  
K × 8) Static RAM  
Features  
Functional Description  
Temperature Ranges  
Industrial: –40 °C to 85 °C  
Automotive-A: –40 °C to 85 °C  
The CY7C1019CV33 is a high performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), an active LOW  
Output Enable (OE), and tristate drivers. This device has an  
automatic power down feature that significantly reduces power  
consumption when deselected.  
Pin and Function compatible with CY7C1019BV33  
High Speed  
tAA = 10 ns  
Writing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. Data on the eight I/O pins  
(I/O0 through I/O7) is then written into the location specified on  
the address pins (A0 through A16).  
CMOS for optimum Speed and Power  
Data Retention at 2.0 V  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins will appear on the I/O pins.  
Center Power/Ground Pinout  
Automatic Power Down when deselected  
Easy Memory Expansion with CE and OE Options  
Available in Pb-free 32-pin TSOP II package  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high impedance state when the device is deselected (CE HIGH),  
the outputs are disabled (OE HIGH), or during a write operation  
(CE LOW, and WE LOW).  
Logic Block Diagram  
I/O  
0
INPUT BUFFER  
I/O  
1
A
0
A
A
2
1
I/O  
2
A
3
A
I/O  
3
4
128K x 8  
ARRAY  
A
5
A
6
I/O  
4
A
7
A
8
I/O  
5
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
7
OE  
Cypress Semiconductor Corporation  
Document #: 38-05130 Rev. *K  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 8, 2011  
[+] Feedback  

与CY7C1019CV33_11相关器件

型号 品牌 获取价格 描述 数据表
CY7C1019CV33_12 CYPRESS

获取价格

1-Mbit (128 K × 8) Static RAM
CY7C1019CV33-10VC CYPRESS

获取价格

128K x 8 Static RAM
CY7C1019CV33-10VCT ROCHESTER

获取价格

128KX8 STANDARD SRAM, 10ns, PDSO32, 0.400 INCH, SOJ-32
CY7C1019CV33-10VCT CYPRESS

获取价格

Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, SOJ-32
CY7C1019CV33-10VI CYPRESS

获取价格

128K x 8 Static RAM
CY7C1019CV33-10VIT CYPRESS

获取价格

Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
CY7C1019CV33-10ZC CYPRESS

获取价格

128K x 8 Static RAM
CY7C1019CV33-10ZI CYPRESS

获取价格

128K x 8 Static RAM
CY7C1019CV33-10ZXA CYPRESS

获取价格

1-Mbit (128 K × 8) Static RAM Center Power/Gr
CY7C1019CV33-10ZXAT CYPRESS

获取价格

1-Mbit (128 K × 8) Static RAM Center Power/Gr