Datasheet > CY7C1019B-15ZCT

CY7C1019B-15ZCT

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
8页	408K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, TSOP2-32

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1019B-15ZCT 数据手册

CY7C1019B

CY7C10191B

AC Test Loads and Waveforms

R1 480Ω

ALL INPUT PULSES

90%

10%

R1 480Ω

OUTPUT

3.0V

GND

90%

10%

OUTPUT

255Ω

30 pF

5 pF

≤ 3 ns

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

(b)

(a)

Equivalent to: THÉVENIN EQUIVALENT

167Ω

1.73V

OUTPUT

Switching Characteristics^[4]Over the Operating Range

7C10191B-10

7C1019B-12

7C1019B-15

Min. Max.

Parameter

Read Cycle

t_RC

Description

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

t_AA

Address to Data Valid

t_OHA

Data Hold from Address Change

t_ACE

LOW to Data Valid

LOW to Low Z

HIGH to High Z^{[5, 6]}

LOW to Low Z^[6]

HIGH to High Z^{[5, 6]}

LOW to Power-Up

HIGH to Power-Down

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

t_PD

Write Cycle^{[7, 8]}

t_WC

t_SCE

t_AW

t_HA

Write Cycle Time

LOW to Write End

Address Set-Up to Write End

Address Hold from Write End

Address Set-Up to Write Start

t_SA

t_PWE

t_SD

Pulse Width

Data Set-Up to Write End

t_HD

Data Hold from Write End

HIGH to Low Z^[6]

t_LZWE

t_HZWE

LOW to High Z^{[5, 6]}

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

/I and 30-pF load capacitance.

OL OH

5. t

, t

, and t

are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

HZOE HZCE

HZWE

6. At any given temperature and voltage condition, t

is less than t

, t

is less than t

, and t

is less than t

for any given device.

LZWE

HZCE

LZCE HZOE

LZOE

HZWE

7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any

of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t

and t

HZWE

Document #: 38-05026 Rev. *B

Page 3 of 8

1 234 5 6 7 8

下载PDF

与CY7C1019B-15ZCT相关器件

型号	品牌	描述	获取价格	数据表
CY7C1019B-15ZI	CYPRESS	128K x 8 Static RAM	获取价格
CY7C1019B-15ZXC	CYPRESS	128K x 8 Static RAM	获取价格
CY7C1019B-15ZXCT	CYPRESS	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, LEAD FREE, TSOP2-32	获取价格
CY7C1019BN	CYPRESS	128K x 8 Static RAM	获取价格
CY7C1019BN-12VC	CYPRESS	128K x 8 Static RAM	获取价格
CY7C1019BN-12VCT	CYPRESS	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, SOJ-32	获取价格