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CY7C09369V-6AXC PDF预览

CY7C09369V-6AXC

更新时间： 2024-02-24 09:11:46
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 静态存储器内存集成电路
页数 文件大小 规格书
20页 1231K
描述
16KX18 DUAL-PORT SRAM, 6.5ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C09369V-6AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LEAD FREE, PLASTIC, MS-026, TQFP-100针数：100
Reach Compliance Code：unknown风险等级：5.78
Is Samacsys：N最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码：S-PQFP-G100
JESD-609代码：e3/e4长度：14 mm
内存密度：294912 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16KX18
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C09369V-6AXC 数据手册

 浏览型号CY7C09369V-6AXC的Datasheet PDF文件第2页浏览型号CY7C09369V-6AXC的Datasheet PDF文件第3页浏览型号CY7C09369V-6AXC的Datasheet PDF文件第4页浏览型号CY7C09369V-6AXC的Datasheet PDF文件第6页浏览型号CY7C09369V-6AXC的Datasheet PDF文件第7页浏览型号CY7C09369V-6AXC的Datasheet PDF文件第8页 
CY7C09269V/79V/89V  
CY7C09369V/79V/89V  
Pin Definitions  
Left Port  
A0L–A15L  
ADSL  
Right Port  
Description  
A0R–A15R  
ADSR  
Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).  
Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access  
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter  
with the address present on the address pins.  
CE0L, CE1L CE0R,CE1R  
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their  
active states (CE0 ≤ VIL and CE1 ≥ VIH).  
CLKL  
CLKR  
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.  
CNTENL  
CNTENR  
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its  
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.  
CNTRSTL  
CNTRSTR  
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective  
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.  
I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).  
LBL  
LBR  
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower  
byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both the LB and  
OE signals must be asserted to drive output data on the lower byte of the data pins.  
UBL  
OEL  
UBR  
OER  
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).  
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read  
operations.  
R/WL  
R/WR  
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For  
read operations, assert this pin HIGH.  
FT/PIPEL  
FT/PIPER  
Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For  
pipelined mode operation, assert this pin HIGH.  
GND  
NC  
Ground Input.  
No Connect.  
Power Input.  
VCC  
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down  
Functional Description  
the internal circuitry to reduce the static power consumption. The  
use of multiple Chip Enables enables easier banking of multiple  
chips for depth expansion configurations. In the pipelined mode,  
one cycle is required with CE0 LOW and CE1 HIGH to reactivate  
the outputs.  
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are  
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18  
dual-port static RAMs. Two ports are provided, permitting  
independent, simultaneous access for reads and writes to any  
location in memory[11]. Registers on control, address, and data  
lines allow for minimal setup and hold times. In pipelined output  
mode, data is registered for decreased cycle time. Clock to data  
valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow through mode can also  
be used to bypass the pipelined output register to eliminate  
Counter enable inputs are provided to stall the operation of the  
address input and use the internal address generated by the  
internal counter for fast interleaved memory applications. A  
port’s burst counter is loaded with the port’s Address Strobe  
(ADS). When the port’s Count Enable (CNTEN) is asserted, the  
address counter increments on each LOW to HIGH transition of  
that port’s clock signal. This reads/writes one word from or into  
each successive address location, until CNTEN is deasserted.  
The counter can address the entire memory array and loop back  
to the start. Counter Reset (CNTRST) is used to reset the burst  
counter.  
access latency. In flow through mode, data is available tCD1  
18 ns after the address is clocked into the device. Pipelined  
output or flow through mode is selected through the FT/Pipe pin.  
=
Each port contains a burst counter on the input address register.  
The internal write pulse width is independent of the LOW to HIGH  
transition of the clock signal. The internal write pulse is self timed  
to allow the shortest possible cycle times.  
All parts are available in 100-pin Thin Quad Plastic Flatpack  
(TQFP) packages.  
Note  
11. When writing simultaneously to the same location, the final value cannot be guaranteed.  
Document #: 38-06056 Rev. *C  
Page 4 of 19  
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