Datasheet > CY7C037

CY7C037

更新时间： 2024-11-09 00:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	258K
描述
32K/64K x 16/18 Dual-Port Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C037 数据手册

25/0251

CY7C027/028

CY7C037/038

32K/64K x 16/18

Dual-Port Static RAM

• Fully asynchronous operation

Features

• Automatic power-down

• Expandable data bus to 32/36 bits or more using Mas-

ter/Slave chip select when using more than one device

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 32K x 16 organization (CY7C027)

• 64K x 16 organization (CY7C028)

• 32K x 18 organization (CY7C037)

• 64K x 18 organization (CY7C038)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12^[1]/15/20 ns

• Low operating power

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flags for port-to-port communication

• Separate upper-byte and lower-byte control

• Dual Chip Enables

• Pin select for Master or Slave

— Active: I_CC= 180 mA (typical)

• Commercial and industrial temperature ranges

• Available in 100-pin TQFP

— Standby: I_SB3= 0.05 mA (typical)

• Pin-compatible and functionally equivalent to IDT7027

Logic Block Diagram

R/W_L

UB_L

R/W_R

UB_R

CE_0L

CE_0R

CE_1L

CE_1R

CE_L

CE_R

LB_L

LB_R

OE_L

OE_R

8/9

[2]

8/9

[2]

I/O_8/9L–I/O_15/17L

I/O_8/9L–I/O_15/17R

8/9

[3]

I/O

Control

I/O

Control

I/O_0L–I/O_7/8L

I/O_0L–I/O_7/8R

15/16

[4]

15/16

[4]

Address

Decode

Address

Decode

True Dual-Ported

A_0L–A

_0R–A_14/15R

14/15L

RAM Array

15/16

[4]

A_0L–A

A_0R–A_14/15R

14/15L

CE_L

CE_R

Interrupt

Semaphore

Arbitration

OE_L

OE_R

R/W_L

SEM_L

BUSY_L^[5]

R/W_R

SEM_R

^[5]BUSY_R

INT_R

INT_L

UB_L

UB_R

LB_L

M/S

LB_R

Notes:

1. See page 6 for Load Conditions.

2. I/O₈–I/O₁₅for x16 devices; I/O₉–I/O₁₇for x18 devices.

3. I/O₀–I/O₇for x16 devices; I/O₀–I/O₈for x18 devices.

4. A₀–A₁₄for 32K; A₀–A₁₅for 64K devices.

5. BUSY is an output in master mode and an input in slave mode.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06042 Rev. *A

Revised December 27, 2002

12 3 4 5 6 7...19

中文翻译

下载PDF

与CY7C037相关器件

型号	品牌	获取价格	描述	数据表
CY7C037-12AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C037-15AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C037-20AC	CYPRESS	获取价格	32K/64K x 16/18 Dual-Port Static RAM
CY7C037AV-20AXC	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM
CY7C037AV-20AXI	CYPRESS	获取价格	3.3 V 32 K / 64 K Ã 16 / 18 Dual-Port Static
CY7C037V	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM
CY7C037V-15AC	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM
CY7C037V-15ACT	CYPRESS	获取价格	Dual-Port SRAM, 32KX18, 15ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
CY7C037V-15AXC	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM
CY7C037V-20AC	CYPRESS	获取价格	3.3V 32K/64K x 16/18 Dual-Port Static RAM