Datasheet > CY7B992-2

CY7B992-2

更新时间： 2024-11-16 23:16:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
15页	290K
描述
Programmable Skew Clock Buffer

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CY7B992-2 数据手册

CY7B991

CY7B992

Programmable Skew Clock Buffer

functions. These multiple-output clock drivers provide the sys-

tem integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual driv-

ers, arranged as four pairs of user-controllable outputs, can

each drive terminated transmission lines with impedances as

low as 50Ω while delivering minimal and specified output skews

and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 80-MHz output operation

• User-selectable output functions

— Selectable skew to 18 ns

— Inverted and non-inverted

— Operation at ¹⁄₂and ¹⁄₄input frequency

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs able to skew up

to ±6 time units from their nominal “zero” skew position. The com-

pletely integrated PLL allows external load and transmission line

delay effects to be canceled. When this “zero delay”capability of the

PSCB is combined with the selectable output skew functions, the

user can create output-to-output delays of up to ±12 time units.

— Operation at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

• Outputs drive 50Ω terminated lines

• Low operating current

• 32-pin PLCC/LCC package

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility mini-

mizes clock distribution difficulty while allowing maximum sys-

tem clock speed and flexibility.

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buff-

ers (PSCB) offer user-selectable control over system clock

Logic Block Diagram

Pin Configuration

TEST

PLCC/LCC

PHASE

FREQ

DET

VCO AND

TIME UNIT

GENERATOR

FILTER

REF

32 31 30

2F0

GND

1F1

1F0

3F1

4F0

4Q0

4Q1

4F0

4F1

SELECT

INPUTS

(THREE

LEVEL)

CCQ

CY7B991

CY7B992

CCN

SKEW

SELECT

MATRIX

CCN

3Q0

3Q1

3F0

3F1

4Q1

1Q0

1Q1

GND

4Q0

GND

2Q0

2Q1

2F0

2F1

14 15 16 17 18 19 20

1Q0

1Q1

1F0

1F1

7B991–2

7B991–1

Pentium is a trademark of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07138 Rev. **

Revised September 26, 2001

12 3 4 5 6 7...15

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与CY7B992-2相关器件

型号	品牌	获取价格	描述	数据表
CY7B992-2JC	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-2JCT	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JC	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JCT	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JI	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JI[27]	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JIT	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JXI	CYPRESS	获取价格	Programmable Skew Clock Buffer
CY7B992-5JXIT	CYPRESS	获取价格	Programmable Skew Clock Buffer

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