CY7B9930V-5AI

更新时间： 2024-09-30 05:09:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	156K
描述
High-Speed Multi-Frequency PLL Clock Buffer

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CY7B9930V-5AI 数据手册

RoboClockII™ Junior

CY7B9930V

CY7B9940V

High-Speed Multi-Frequency PLL Clock Buffer

Features

Functional Description

• 12–100MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)

input/output operation

• Matched pair output skew < 200 ps

• Zero input-to-output delay

• 10 LVTTL 50% duty-cycle outputs capable of driving

50ω terminated lines

The CY7B9930V and CY7B9940V High-Speed Multi-

Frequency PLL Clock Buffers offer user-selectable control

over system clock functions. This multiple-output clock driver

provides the system integrator with functions necessary to

optimize the timing of high-performance computer or commu-

nication systems.

Ten configurable outputs can each drive terminated trans-

mission lines with impedances as low as 50Ω while delivering

minimal and specified output skews at LVTTL levels. The outputs

are arranged in three banks. The FB feedback bank consists

of two outputs, which allows divide-by functionality from 1 to

12. Any one of these ten outputs can be connected to the

feedback input as well as driving other inputs.

• Commercial temp. range with eight outputs at 200 MHz

• Industrial temp. range with eight outputs at 200 MHz

• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and

hot insertable reference inputs

• Multiply ratios of (1–6, 8, 10, 12)

• Operation up to 12x input frequency

• Individual output bank disable for aggressive power

management and EMI reduction

• Output high-impedance option for testing purposes

• Fully integrated PLL with lock indicator

• Low cycle-to-cycle jitter (<100 ps peak-peak)

• Single 3.3V ± 10% supply

Selectable reference input is a fault tolerance feature that

allows smooth change over to secondary clock source, when

the primary clock source is not in operation. The reference

inputs are configurable to accommodate both LVTTL or Differ-

ential (LVPECL) inputs. The completely integrated PLL

reduces jitter and simplifies board layout.

• 44-pin TQFP package

Functional Block Diagram

Pin Configuration

44-Pin TQFP

FBKA

LOCK

Control Logic

Divide

Generator

Phase

Freq.

Detector

VCO

Filter

REFA+

REFA–

REFB+

REFB–

44 43 42 41 40 39 38 37 36 35 34

Output_Mode

REFSEL

GND

2QB1

VCCN

2QB0

GND

VCCQ

REFA+

REFA –

REFSEL

REFB–

REFB+

QFA0

QFA1

Divide

Matrix

FBDS0

FBDS1

Feedback Bank

Bank 2

CY7B9930V/40V

GND

2QA0

2QA1

VCCN

2QA0

GND

2QB0

2QB1

VCCQ

DIS2

DIS1

GND

DIS1

1QA0

1QA1

12 13

14 15

16 17 18

20 21

Bank 1

1QB0

1QB1

Cypress Semiconductor Corporation

Document #: 38-07271 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 25, 2002

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CY7B9930V-5AI 替代型号

型号	品牌	替代类型	描述	数据表
CY7B9930V-5AC	CYPRESS	功能相似	High-Speed Multi-Frequency PLL Clock Buffer

与CY7B9930V-5AI相关器件

型号	品牌	获取价格	描述	数据表
CY7B9930V-5AXC	CYPRESS	获取价格	High Speed Multifrequency PLL Clock Buffer
CY7B9930V-5AXCT	CYPRESS	获取价格	High Speed Multifrequency PLL Clock Buffer
CY7B993V	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V_05	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V_11	CYPRESS	获取价格	High Speed Multi Phase PLL Clock Buffer
CY7B993V-2AC	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-2ACT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AI	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-2AIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer

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