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CY7B9940V-2AC PDF预览

CY7B9940V-2AC

更新时间: 2024-09-30 05:09:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
9页 156K
描述
High-Speed Multi-Frequency PLL Clock Buffer

CY7B9940V-2AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-44
针数:44Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.67其他特性:CONFIGURABLE AS SINGLE ENDED TTL ALSO
系列:7B输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G44JESD-609代码:e0
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.03 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:44实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
传播延迟(tpd):0.25 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.65 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
最小 fmax:200 MHzBase Number Matches:1

CY7B9940V-2AC 数据手册

 浏览型号CY7B9940V-2AC的Datasheet PDF文件第2页浏览型号CY7B9940V-2AC的Datasheet PDF文件第3页浏览型号CY7B9940V-2AC的Datasheet PDF文件第4页浏览型号CY7B9940V-2AC的Datasheet PDF文件第5页浏览型号CY7B9940V-2AC的Datasheet PDF文件第6页浏览型号CY7B9940V-2AC的Datasheet PDF文件第7页 
RoboClockII™ Junior  
CY7B9930V  
CY7B9940V  
High-Speed Multi-Frequency PLL Clock Buffer  
Features  
Functional Description  
• 12–100MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)  
input/output operation  
• Matched pair output skew < 200 ps  
• Zero input-to-output delay  
• 10 LVTTL 50% duty-cycle outputs capable of driving  
50ω terminated lines  
The CY7B9930V and CY7B9940V High-Speed Multi-  
Frequency PLL Clock Buffers offer user-selectable control  
over system clock functions. This multiple-output clock driver  
provides the system integrator with functions necessary to  
optimize the timing of high-performance computer or commu-  
nication systems.  
Ten configurable outputs can each drive terminated trans-  
mission lines with impedances as low as 50while delivering  
minimal and specified output skews at LVTTL levels. The outputs  
are arranged in three banks. The FB feedback bank consists  
of two outputs, which allows divide-by functionality from 1 to  
12. Any one of these ten outputs can be connected to the  
feedback input as well as driving other inputs.  
• Commercial temp. range with eight outputs at 200 MHz  
• Industrial temp. range with eight outputs at 200 MHz  
• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and  
hot insertable reference inputs  
• Multiply ratios of (1–6, 8, 10, 12)  
• Operation up to 12x input frequency  
• Individual output bank disable for aggressive power  
management and EMI reduction  
• Output high-impedance option for testing purposes  
• Fully integrated PLL with lock indicator  
• Low cycle-to-cycle jitter (<100 ps peak-peak)  
• Single 3.3V ± 10% supply  
Selectable reference input is a fault tolerance feature that  
allows smooth change over to secondary clock source, when  
the primary clock source is not in operation. The reference  
inputs are configurable to accommodate both LVTTL or Differ-  
ential (LVPECL) inputs. The completely integrated PLL  
reduces jitter and simplifies board layout.  
• 44-pin TQFP package  
Functional Block Diagram  
Pin Configuration  
44-Pin TQFP  
FBKA  
LOCK  
Control Logic  
Divide  
Generator  
Phase  
Freq.  
Detector  
VCO  
Filter  
FS  
REFA+  
REFA–  
REFB+  
3
3
REFB–  
44 43 42 41 40 39 38 37 36 35 34  
Output_Mode  
REFSEL  
GND  
2QB1  
VCCN  
2QB0  
GND  
1
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
VCCQ  
REFA+  
REFA –  
REFSEL  
REFB–  
REFB+  
FS  
2
3
QFA0  
QFA1  
Divide  
Matrix  
3
3
FBDS0  
FBDS1  
Feedback Bank  
Bank 2  
4
5
CY7B9930V/40V  
GND  
6
2QA0  
2QA1  
2QA1  
VCCN  
2QA0  
GND  
7
8
GND  
2QB0  
2QB1  
9
VCCQ  
DIS2  
10  
11  
DIS2  
DIS1  
GND  
DIS1  
1QA0  
1QA1  
12 13  
14 15  
22  
16 17 18  
20 21  
19  
Bank 1  
1QB0  
1QB1  
Cypress Semiconductor Corporation  
Document #: 38-07271 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised July 25, 2002  
[+] Feedback  

CY7B9940V-2AC 替代型号

型号 品牌 替代类型 描述 数据表
CY7B9940V-2AXI CYPRESS

完全替代

High Speed Multifrequency PLL Clock Buffer
CY7B9940V-2AXCT CYPRESS

完全替代

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CY7B9940V-2AXC CYPRESS

完全替代

High Speed Multifrequency PLL Clock Buffer

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