Datasheet > CY7B9945V_11

CY7B9945V_11

更新时间： 2024-09-30 09:43:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
15页	417K
描述
High Speed Multi-phase PLL Clock Buffer

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CY7B9945V_11 数据手册

RoboClock^®

CY7B9945V

PRELIMINARY

High Speed Multi-phase PLL Clock Buffer

Features

Functional Description

■ 500 ps max Total Timing Budget (TTB™) window

■ 24 MHz –200 MHz input and Output Operation

■ Low Output-output skew <200 ps

The CY7B9945V high speed multi-phase PLL clock buffer offers

user selectable control over system clock functions. This multiple

output clock driver provides the system integrator with functions

necessary to optimize the timing of high performance computer

and communication systems.

■ 10 + 1 LVTTL outputs driving 50Ω terminated lines

■ Dedicated feedback output

The device features a guaranteed maximum TTB window speci-

fying all occurrences of output clocks. This includes the input

reference clock across variations in output frequency, supply

voltage, operating temperature, input edge rate, and process.

■ Phase adjustments in 625ps/1300 ps steps up to +10.4 ns

■ 3.3 V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable

Reference Inputs

Ten configurable outputs each drive terminated transmission

lines with impedances as low as 50Ω while delivering minimal

and specified output skews at LVTTL levels. The outputs are

arranged in two banks of four and six outputs. These banks

enable a divide function of 1 to 12, with phase adjustments in 625

ps–1300 ps increments up to ±10.4 ns. The dedicated feedback

output enables divide-by functionality from 1 to 12 and limited

phase adjustments. However, if needed, any one of the ten

outputs can be connected to the feedback input as well as driving

other inputs.

■ Multiply or Divide Ratios of 1 through 6, 8, 10, and 12

■ Individual Output Bank Disable

■ Output High Impedance Option for Testing Purposes

■ Integrated Phase Locked Loop (PLL) with Lock Indicator

■ Low Cycle-cycle jitter (<100 ps peak-peak)

■ 3.3 V Operation

Selectable reference input is a fault tolerant feature that enables

smooth change over to a secondary clock source when the

primary clock source is not in operation. The reference inputs

and feedback inputs are configurable to accommodate both

LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

■ Industrial Temperature Range: –40 °C to +85 °C

■ 52-pin 1.4 mm TQFP package

Logic Block Diagram

F S

R E F A +

R E F A -

L O C K

R E F B +

R E F B -

P L L

R E F S E L

F B K

M O D E

D iv id e

a n d

F B F 0

Q F

P h a s e

S e le c t

F B D S 0

F B D S 1

1 Q 0

1 Q 1

1 F 0

1 F 1

D iv id e

a n d

P h a s e

S e le c t

1 D S 0

1 D S 1

1 Q 2

1 F 2

1 F 3

1 Q 3

D IS 1

2 Q 0

2 Q 1

2 F 0

2 F 1

D iv id e

a n d

P h a s e

S e le c t

2 Q 2

2 Q 3

2 Q 4

2 D S 0

2 D S 1

2 Q 5

D IS 2

Cypress Semiconductor Corporation

Document Number: 38-07336 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 15, 2011

[+] Feedback

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中文翻译

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与CY7B9945V_11相关器件

型号	品牌	获取价格	描述	数据表
CY7B9945V-2AC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B9945V-2AI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B9945V-2AIT	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer
CY7B9945V-2AXC	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer
CY7B9945V-2AXCT	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer
CY7B9945V-2AXI	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer
CY7B9945V-2AXIT	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer
CY7B9945V-5AC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B9945V-5AI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B9945V-5AXC	CYPRESS	获取价格	High Speed Multi-phase PLL Clock Buffer

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