CY7B994V-2BBXCT

更新时间： 2024-09-30 03:13:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
15页	392K
描述
High-speed Multi-phase PLL Clock Buffer

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技术参数
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CY7B994V-2BBXCT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA100,10X10,40	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.51
其他特性：	CONFIGURABLE AS SINGLE ENDED TTL ALSO	系列：	7B
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PBGA-B100
JESD-609代码：	e1	长度：	11 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.002 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	100
实输出次数：	16	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA100,10X10,40	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.25 ns
传播延迟（tpd）：	0.25 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.8 ns	座面最大高度：	1.4 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.97 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	11 mm
最小 fmax：	200 MHz

CY7B994V-2BBXCT 数据手册

RoboClock^

CY7B993V

CY7B994V

High-speed Multi-phase PLL Clock Buffer

Features

Functional Description

• 500-ps max. Total Timing Budget™ (TTB™) window

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user-selectable control over system clock

functions. This multiple-output clock driver provides the

system integrator with functions necessary to optimize the

timing of high-performance computer and communication

systems.

• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)

input/output operation

• Matched pair output skew < 200 ps

• Zero input-to-output delay

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

Eighteen configurable outputs each drive terminated trans-

mission lines with impedances as low as 50Ω while delivering

minimal and specified output skews at LVTTL levels. The outputs

are arranged in five banks. Banks 1 to 4 of four outputs allow

a divide function of 1 to 12, while simultaneously allowing

phase adjustments in 625–1300-ps increments up to 10.4 ns.

One of the output banks also includes an independent clock

invert function. The feedback bank consists of two outputs,

which allows divide-by functionality from 1 to 12 and limited

phase adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

• 18 LVTTL outputs driving 50Ω terminated lines

• 16 outputs at 200 MHz: Commercial temperature

• 6 outputs at 200 MHz: Industrial temperature

• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable

reference inputs

• Phaseadjustmentsin625-/1300-psstepsupto±10.4 ns

• Multiply/divide ratios of 1–6, 8, 10, 12

• Individual output bank disable

• Output high-impedance option for testing purposes

• Fully integrated phase-locked loop (PLL) with lock

indicator

• <50-ps typical cycle-to-cycle jitter

• Single 3.3V ± 10% supply

• 100-pin TQFP package

Selectable reference input is a fault tolerance feature that

allows smooth change-over to secondary clock source, when

the primary clock source is not in operation. The reference

inputs and feedback inputs are configurable to accommodate

both LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

• 100-lead BGA package

FBKA+

Functional

FBKA–

LOCK

FBKB+

Block Diagram

FBKB–

Control Logic

VCO

Phase

FBSEL

Freq.

Divide and Phase

Generator

Filter

REFA+

REFA–

Detector

REFB+

REFB–

REFSEL

OUTPUT_MODE

Divide and

Phase

FBF0

QFA0

QFA1

FBDS0

FBDS1

FBDIS

Feedback Bank

Bank 4

Select

Matrix

4QA0

4QA1

4F0

Divide and

Phase

4F1

4DS0

4DS1

DIS4

4QB0

4QB1

Select

Matrix

3QA0

3QA1

3F0

3F1

3DS0

3DS1

DIS3

INV3

Divide and

Phase

Bank 3

Bank 2

Select

3QB0

3QB1

Matrix

2QA0

2QA1

2F0

Divide and

Phase

2F1

2DS0

2DS1

DIS2

Select

2QB0

2QB1

Matrix

1QA0

1QA1

1F0

1F1

1DS0

1DS1

DIS1

Divide and

Phase

Bank 1

Select

1QB0

1QB1

Matrix

Cypress Semiconductor Corporation

Document #: 38-07127 Rev. *F

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 10, 2005

12 3 4 5 6 7...15

中文翻译

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CY7B994V-2BBXI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-2BBXIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AC	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B994V-5ACT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AI	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B994V-5AIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AXC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AXCT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AXI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B994V-5AXIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer

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