Datasheet > CY7B9950_07

CY7B9950_07

更新时间： 2024-09-30 05:09:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		多相元件时钟
页数	文件大小	规格书
12页	331K
描述
2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer

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CY7B9950_07 数据手册

RoboClock^®, CY7B9950

2.5/3.3V, 200 MHz High-Speed

Multi-Phase PLL Clock Buffer

Features

■ 2.5V or 3.3V operation

Description

The CY7B9950 RoboClock^®is a low voltage, low power,

eight-output, 200 MHz clock driver. It features output phase

programmability which is necessary to optimize the timing of

high performance computer and communication systems.

■ Split output bank power supplies

■ Output frequency range: 6 MHz to 200 MHz

■ 50 ps typical matched-pair Output-output skew

■ 50 ps typical Cycle-cycle jitter

The user can program the phase of the output banks through

nF[0:1] pins. The adjustable phase feature allows the user to

skew the outputs to lead or lag the reference clock. Any one

of the outputs can be connected to the feedback input to

achieve different reference frequency multiplications, and

divide ratios and zero input-output delay.

■ 49.5/50.5% typical output duty cycle

■ Selectable output drive strength

■ Selectable positive or negative edge synchronization

■ Eight LVTTL outputs driving 50 Ω terminated lines

■ LVCMOS/LVTTL over-voltage-tolerant reference input

■ Phase adjustments in 625-/1250-ps steps up to +7.5 ns

■ 2x, 4x multiply and (1/2)x, (1/4)x divide ratios

■ Spread-Spectrum compatible

The device also features split output bank power supplies,

which enable the user to run two banks (1Qn and 2Qn) at a

power supply level different from that of the other two banks

(3Qn and 4Qn). Additionally, the three-level PE/HD pin

controls the synchronization of the output signals to either the

rising, or the falling edge of the reference clock and selects the

drive strength of the output buffers. The high drive option

(PE/HD = MID) increases the output current from ± 12 mA to

± 24 mA(3.3V).

■ Industrial temp. range: –40°C to +85°C

■ 32-pin TQFP package

Logic Block Diagram

TEST PE/HD

VDDQ1

REF

PLL

1Q0

1Q1

Phase

Select

1F1:0

2Q0

2Q1

Phase

Select

2F1:0

3F1:0

4F1:0

3Q0

3Q1

Phase

Select

and /K

VDDQ3

4Q0

Phase

Select

and /M

4Q1

VDDQ4 sOE#

Cypress Semiconductor Corporation

Document #: 38-07338 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 27, 2007

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与CY7B9950_07相关器件

型号	品牌	获取价格	描述	数据表
CY7B9950AC	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950ACT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AI	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AI	ROCHESTER	获取价格	PLL Based Clock Driver,
CY7B9950AIT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AXC	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AXCT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AXI	CYPRESS	获取价格	2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AXIT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950V-5AXC	CYPRESS	获取价格	2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer

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