CY7B995

更新时间： 2024-09-30 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		多相元件时钟
页数	文件大小	规格书
11页	285K
描述
2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer

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CY7B995 数据手册

CY7B995

2.5/3.3V 200-MHz High-Speed Multi-Phase

PLL Clock Buffer

Features

Description

• 2.5V or 3.3V operation

• Split output bank power supplies

• Output frequency range: 6 MHz to 200 MHz

• Output-output skew < 100 ps

• Cycle-cycle jitter <100 ps

• ± 2% max output duty cycle

• Selectable output drive strength

• Selectable positive or negative edge synchronization

• Eight LVTTL outputs driving 50Ω terminated lines

• LVCMOS/LVTTL over-voltage tolerant reference input

The CY7B995 RoboClock is a low-voltage, low-power,

eight-output, 200-MHz clock driver. It features output phase

programmability which is necessary to optimize the timing of

high-performance computer and communication systems.

The user can program both the frequency and the phase of the

output banks through nF[0:1] and DS[0:1] pins. The adjustable

phase feature allows the user to skew the outputs to lead or

lag the reference clock. Any one of the outputs can be con-

nected to feedback input to achieve different reference fre-

quency multiplication and divide ratios and zero input-output

delay.

The device also features split output bank power supplies

which enable the user to run two banks (1Qn and 2Qn) at a

power supply level different from that of the other two banks

(3Qn and 4Qn). Additionally, the three-level PE/HD pin con-

trols the synchronization of the output signals to either the ris-

ing or the falling edge of the reference clock and selects the

drive strength of the output buffers. The high drive option

(PE/HD = MID) increases the output current from ± 12 mA to

± 24 mA

• Selectable phase-locked loop (PLL) frequency range

and lock indicator

• Phase adjustments in 625/1250 ps steps up to ± 7.5 ns

• (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios

• Spread-Spectrum-compatible

• Power-down mode

• Selectable reference divider

(3.3V).

• Industrial temperature range: -40°C to +85°C

• 44-pin TQFP package

Block Diagram

Pin Configuration

TEST PE/HD FS VDDQ1

PD#/DIV

REF

LOCK

PLL

44 43 42 41 40 39 38 37 36 35 34

33 1F0

4F1

sOE#

DS1

DS0

LOCK

VDDQ1

DS1:0

PD#/DIV

PE/HD

VDDQ4

1Q0

1Q1

Phase

Select

1F1:0

CY7B995

28 VDDQ1

VDDQ4

4Q1

2Q0

2Q1

1Q0

Phase

Select

2F1:0

3F1:0

4F1:0

4Q0

VSS

1Q1

VSS

3Q0

Phase

Select

and /K

3Q1

12 13 14 15 16 17 18 19 20 21 22

VDDQ3

4Q0

Phase

Select

and /M

4Q1

sOE#

VDDQ4

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07337 Rev. *A

Revised February 24, 2004

12 3 4 5 6 7...11

中文翻译

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与CY7B995相关器件

型号	品牌	获取价格	描述	数据表
CY7B995_07	CYPRESS	获取价格	2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B995_11	CYPRESS	获取价格	2.5/3.3 V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950_06	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950_07	CYPRESS	获取价格	2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AC	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950ACT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AI	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AI	ROCHESTER	获取价格	PLL Based Clock Driver,
CY7B9950AIT	CYPRESS	获取价格	2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer

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