Datasheet > CY7B993V_11

CY7B993V_11

更新时间： 2024-09-30 09:43:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
18页	570K
描述
High Speed Multi Phase PLL Clock Buffer

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CY7B993V_11 数据手册

RoboClock^

CY7B993V, CY7B994V

High Speed Multi Phase PLL Clock Buffer

Features

Functional Description

■ 500 ps Max Total Timing Budget (TTB™) window

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user selectable control over system clock

functions. This multiple output clock driver provides the system

integrator with functions necessary to optimize the timing of

high-performance computer and communication systems.

■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz

(CY7B994V) Input/Output Operation

■ Matched Pair Output Skew < 200 ps

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

■ Zero Input-to-Output Delay

■ 18 LVTTL Outputs Driving 50 Terminated Lines

■ 16 Outputs at 200 MHz: Commercial Temperature

■ 6 Outputs at 200 MHz: Industrial Temperature

Eighteen configurable outputs each drive terminated

transmission lines with impedances as low as 50while delivering

minimal and specified output skews at LVTTL levels. The outputs are

arranged in five banks. Banks 1 to 4 of four outputs allow a divide

function of 1 to 12, while simultaneously allowing phase

adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One

of the output banks also includes an independent clock invert

function. The feedback bank consists of two outputs, which

allows divide-by functionality from 1 to 12 and limited phase

adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

■ 3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable

Reference Inputs

■ Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns

■ Multiply/Divide Ratios of 1–6, 8, 10, 12

■ Individual Output Bank Disable

■ Output High Impedance Option for Testing Purposes

■ Fully Integrated Phase Locked Loop (PLL) with Lock Indicator

■ <50-ps Typical Cycle-to-Cycle Jitter

■ Single 3.3V ± 10% Supply

Selectable reference input is a fault tolerance feature that allows

smooth change-over to secondary clock source, when the

primary clock source is not in operation. The reference inputs

and feedback inputs are configurable to accommodate both

LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

■ 100-pin TQFP Package

■ 100-pin BGA Package

Cypress Semiconductor Corporation

Document #: 38-07127 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 26, 2011

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与CY7B993V_11相关器件

型号	品牌	获取价格	描述	数据表
CY7B993V-2AC	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-2ACT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AI	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-2AIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXCT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-5AC	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-5ACT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer

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