CY7B993V-5AI

更新时间： 2024-09-29 22:25:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		多相元件时钟
页数	文件大小	规格书
14页	276K
描述
High-Speed Multi-Phase PLL Clock Buffer

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CY7B993V-5AI 数据手册

RoboClock

CY7B994V

CY7B993V

High-speed Multi-phase PLL Clock Buffer

Features

Functional Description

• 500-ps max. Total Timing Budget™ (TTB™) window

• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)

input/output operation

• Matched pair output skew < 200 ps

• Zero input-to-output delay

• 18 LVTTL outputs driving 50Ω terminated lines

• 16 outputs at 200 MHz: Commercial temperature

• 6 outputs at 200 MHz: Industrial temperature

• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable

reference inputs

• Phaseadjustmentsin625-/1300-psstepsupto±10.4 ns

• Multiply/divide ratios of 1–6, 8, 10, 12

• Individual output bank disable

• Output high-impedance option for testing purposes

• Fully integrated phase-locked loop (PLL) with lock

indicator

• Low cycle-to-cycle jitter (< 100-ps peak-peak)

• Single 3.3V ± 10% supply

• 100-pin TQFP package

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user-selectable control over system clock

functions. This multiple-output clock driver provides the

system integrator with functions necessary to optimize the

timing of high-performance computer and communication

systems.

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

Eighteen configurable outputs each drive terminated trans-

mission lines with impedances as low as 50Ω while delivering

minimal and specified output skews at LVTTL levels. The outputs

are arranged in five banks. Banks 1 to 4 of four outputs allow

a divide function of 1 to 12, while simultaneously allowing

phase adjustments in 625–1300-ps increments up to 10.4 ns.

One of the output banks also includes an independent clock

invert function. The feedback bank consists of two outputs,

which allows divide-by functionality from 1 to 12 and limited

phase adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

• 100-lead BGA package

Selectable reference input is a fault tolerance feature which

allows smooth change over to secondary clock source, when

the primary clock source is not in operation. The reference

inputs and feedback inputs are configurable to accommodate

both LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

FBKA+

Functional

FBKA–

FBKB+

LOCK

Block Diagram

FBKB–

FBSEL

REFA+

REFA–

REFB+

REFB–

Control Logic

VCO

Phase

Freq.

Detector

Divide and Phase

Generator

Filter

OUTPUT_MODE

REFSEL

Divide and

Phase

Select

FBF0

QFA0

QFA1

FBDS0

FBDS1

FBDIS

Feedback Bank

Matrix

4QA0

4QA1

4F0

4F1

4DS0

4DS1

DIS4

Divide and

Phase

Select

Bank 4

Bank 3

Bank 2

4QB0

4QB1

Matrix

3QA0

3QA1

3F0

3F1

3DS0

3DS1

DIS3

INV3

Divide and

Phase

Select

3QB0

3QB1

Matrix

2QA0

2QA1

2F0

2F1

2DS0

2DS1

DIS2

Divide and

Phase

Select

2QB0

2QB1

Matrix

1QA0

1QA1

1F0

Divide and

Phase

Select

1F1

1DS0

1DS1

DIS1

Bank 1

1QB0

1QB1

Matrix

Cypress Semiconductor Corporation

Document #: 38-07127 Rev. *E

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 25, 2003

12 3 4 5 6 7...14

中文翻译

下载PDF

CY7B993V-5AI 替代型号

型号	品牌	替代类型	描述	数据表
CY7B993V-5AC	CYPRESS	完全替代	High-Speed Multi-Phase PLL Clock Buffer
CY7B993V-5AXC	CYPRESS	功能相似	High-speed Multi-phase PLL Clock Buffer
CY7B993V-2AXI	CYPRESS	功能相似	High-speed Multi-phase PLL Clock Buffer

与CY7B993V-5AI相关器件

型号	品牌	获取价格	描述	数据表
CY7B993V-5AIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-5AXC	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-5AXCT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-5AXI	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-5AXIT	CYPRESS	获取价格	High-speed Multi-phase PLL Clock Buffer
CY7B993V-7AC	CYPRESS	获取价格	High-Speed Multi-Phase PLL Clock Buffer
CY7B9940V	CYPRESS	获取价格	High-Speed Multi-Frequency PLL Clock Buffer
CY7B9940V-2AC	CYPRESS	获取价格	High-Speed Multi-Frequency PLL Clock Buffer
CY7B9940V-2ACT	CYPRESS	获取价格	PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), PQFP44, 10 X 10
CY7B9940V-2AI	CYPRESS	获取价格	High-Speed Multi-Frequency PLL Clock Buffer

与CY7B993V-5AI相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

29
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

24
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

25
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

35

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7B993V-5AI

CY7B993V-5AI 数据手册

CY7B993V-5AI 替代型号

与CY7B993V-5AI相关器件

与CY7B993V-5AI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7B993V-5AI

CY7B993V-5AI 数据手册

CY7B993V-5AI 替代型号

与CY7B993V-5AI相关器件

与CY7B993V-5AI相关文章

您还可以找

您在本页遇到什么问题？