RoboClock
CY7B993V
CY7B994V
High-speed Multi-phase PLL Clock Buffer
Features
Functional Description
• 500-ps max. Total Timing Budget™ (TTB™) window
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.
• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated trans-
mission lines with impedances as low as 50Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
• 18 LVTTL outputs driving 50Ω terminated lines
• 16 outputs at 200 MHz: Commercial temperature
• 6 outputs at 200 MHz: Industrial temperature
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
reference inputs
• Phaseadjustmentsin625-/1300-psstepsupto±10.4 ns
• Multiply/divide ratios of 1–6, 8, 10, 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Fully integrated phase-locked loop (PLL) with lock
indicator
• <50-ps typical cycle-to-cycle jitter
• Single 3.3V ± 10% supply
• 100-pin TQFP package
Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
• 100-lead BGA package
FBKA+
Functional
FBKA–
LOCK
FBKB+
Block Diagram
FBKB–
Control Logic
VCO
Phase
FBSEL
Freq.
Divide and Phase
Generator
Filter
FS
REFA+
REFA–
Detector
REFB+
REFB–
REFSEL
3
3
OUTPUT_MODE
Divide and
Phase
FBF0
3
3
3
QFA0
QFA1
FBDS0
FBDS1
FBDIS
Feedback Bank
Bank 4
Select
Matrix
4QA0
4QA1
4F0
3
3
3
3
Divide and
Phase
4F1
4DS0
4DS1
DIS4
4QB0
4QB1
Select
Matrix
3QA0
3QA1
3F0
3F1
3DS0
3DS1
DIS3
INV3
3
3
3
3
Divide and
Phase
Bank 3
Bank 2
Select
3QB0
3QB1
Matrix
3
2QA0
2QA1
3
3
3
3
2F0
Divide and
Phase
2F1
2DS0
2DS1
DIS2
Select
2QB0
2QB1
Matrix
1QA0
1QA1
1F0
1F1
1DS0
1DS1
DIS1
3
3
3
3
Divide and
Phase
Bank 1
Select
1QB0
1QB1
Matrix
Cypress Semiconductor Corporation
Document #: 38-07127 Rev. *F
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 10, 2005