Datasheet > 存储 > SRAM> CY62256L-55SNC

CY62256L-55SNC

更新时间： 2024-11-26 22:18:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	395K
描述
256K (32K x 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62256L-55SNC 数据手册

CY62256

256K (32K x 8) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

—Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• High speed: 55 ns and 70 ns

The CY62256 is a high-performance CMOS static RAM

organized as 32K words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE) and active LOW

output enable (OE) and three-state drivers. This device has an

automatic power-down feature, reducing the power

consumption by 99.9% when deselected.

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location

addressed by the address present on the address pins (A₀

through A₁₄). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

• Voltage range: 4.5V–5.5V operation

• Low active power (70 ns, LL version, Com’l and Ind’l)

— 275 mW (max.)

• Low standby power (70 ns, LL version, Com’l and Ind’l)

— 28 µW (max.)

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Package available in a standard 450-mil-wide (300-mil

body width) 28-lead narrow SOIC, 28-lead TSOP-1,

28-lead reverse TSOP-1, and 600-mil 28-lead PDIP

packages

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.

Logic Block Diagram

I/O

INPUTBUFFER

512 x 512

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05248 Rev. *C

Revised June 25, 2004

12 3 4 5 6 7...12

中文翻译

下载PDF

与CY62256L-55SNC相关器件

型号	品牌	获取价格	描述	数据表
CY62256L-55ZC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-55ZRC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-70PC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-70SNC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-70SNC	ROCHESTER	获取价格	暂无描述
CY62256L-70SNCT	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, SOIC-28
CY62256L-70SNI	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-70SNIT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256L-70SNXC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256L-70SNXC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

与CY62256L-55SNC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

47
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

35
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

64
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

61

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62256L-55SNC

CY62256L-55SNC 数据手册

与CY62256L-55SNC相关器件

与CY62256L-55SNC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62256L-55SNC

CY62256L-55SNC 数据手册

与CY62256L-55SNC相关器件

与CY62256L-55SNC相关文章

您还可以找

您在本页遇到什么问题？