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CY62136CV18LL-70BAIT PDF预览

CY62136CV18LL-70BAIT

更新时间： 2024-02-03 13:35:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 207K
描述
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48

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CY62136CV18LL-70BAIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.82
最长访问时间：70 nsJESD-30 代码：S-PBGA-B48
长度：7 mm内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX16
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：7 mmBase Number Matches：1

CY62136CV18LL-70BAIT 数据手册

 浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第2页浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第3页浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第4页浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第5页浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第6页浏览型号CY62136CV18LL-70BAIT的Datasheet PDF文件第7页 
CY62136CV18 MoBL2™  
128K x 16 Static RAM  
an automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling.  
The device can also be put into standby mode when deselect-  
ed (CE HIGH). The input/output pins (I/O0 through I/O15) are  
placed in a high-impedance state when: deselected (CE  
HIGH), outputs are disabled (OE HIGH), both Byte High En-  
able and Byte Low Enable are disabled (BHE, BLE HIGH), or  
during a write operation (CE LOW and WE LOW).  
Features  
• High Speed  
— 55 ns and 70 ns availability  
• Low voltage range:  
— 1.65V−1.95V  
• Pin Compatible with CY62136BV18  
• Ultra-low active power  
— Typical Active Current: 0.5 mA @ f = 1 MHz  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
— Typical Active Current: 1.5 mA @ f = fmax (70 ns  
speed)  
• Low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O8 to I/O15. See the  
Truth Table at the back of this data sheet for a complete de-  
scription of read and write modes.  
Functional Description  
The CY62136CV18 is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life® (MoBL™) in portable  
applications such as cellular telephones. The device also has  
The CY62136CV18 is available in 48-ball FBGA packaging.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
A
9
8
A
7
A
A
A
A
A
6
128K x 16  
5
4
RAM Array  
2048 X 1024  
I/O –I/O  
0
7
3
2
I/O –I/O  
8
15  
A
1
A
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05016 Rev. *C  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised August 30, 2002  
1234567...12

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