Datasheet > CY28351OC-400T

CY28351OC-400T

更新时间： 2024-02-12 19:38:10

品牌	Logo	应用领域
芯科 - SILICON		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
7页	130K
描述
PLL Based Clock Driver, PDSO48, SSOP-48

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CY28351OC-400T 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	,	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G48	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
端子数量：	48	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

CY28351OC-400T 数据手册

CY28351-400

Differential Clock Buffer/Driver

Description

Features

• Supports 333-MHz and 400-MHz DDR SDRAM

• 60 – 273-MHz operating frequency

This PLL clock buffer is designed for 2.6V_DDand 2.6AV_DD

operation and differential outputs levels.

• Phase-locked loop (PLL) clock distribution for double

data rate synchronous DRAM applications

• Distributes one clock input to ten differential outputs

• External feedback pin (FBIN) is usedtosynchronize the

outputs to the clock input

This device is a zero delay buffer that distributes a clock input

(CLKIN) to ten differential pairs of clock outputs (YT[0:9],

YC[0:9]) and one feedback clock output (FBOUT). The clock

outputs are individually controlled by the serial inputs SCLK

and SDATA.

The two-line serial bus can set each output clock pair (YT[0:9],

YC[0:9]) to the Hi-Z state. When AV_DDis grounded, the PLL is

turned off and bypassed for the test purposes.

• Conforms to the DDRI specification

• Spread Aware™ for electromagnetic interference (EMI)

reduction

The PLL in this device uses the input clock (CLKIN) and the

feedback clock (FBIN) to provide high-performance, low-skew,

low-jitter output differential clocks.

• 48-pin SSOP package

Block Diagram

Pin Configuration

VSS

YC5

VSS

YC0

YT0

YC0

YT1

YC1

YT5

VDDQ

YT6

YT0

VDDQ

YT1

YT2

YC2

YC6

YC1

VSS

YC2

YT3

YC3

SCLK

Serial

Interface

Logic

VSS

YT4

YC4

YC7

SDATA

YT7

YT2

VDDQ

SDATA

YT5

YC5

VDD

SCLK

CLKIN

YT6

YC6

FBIN

VDDQ

CLKIN

FBIN

YT7

YC7

VDDI

AVDD

AVSS

VSS

YC3

FBOUT

PLL

YT8

YC8

VSS

YC8

YT8

YT9

YC9

YT3

VDDQ

YT9

VDDQ

YT4

AVDD

FBOUT

YC9

VSS

YC4

VSS

Rev 1.0, November 28, 2006

Page 1 of 7

www.SpectraLinear.com

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

12 3 4 5 6 7

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与CY28351OC-400T相关器件

型号	品牌	获取价格	描述	数据表
CY28351OCT	CYPRESS	获取价格	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28351OCT	SPECTRALINEAR	获取价格	Differential Clock Buffer/Driver
CY28351OI-400	SILICON	获取价格	PLL Based Clock Driver, PDSO48, SSOP-48
CY28351OI-400T	SILICON	获取价格	Clock Driver
CY28352	SPECTRALINEAR	获取价格	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28352	CYPRESS	获取价格	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28352OC	SPECTRALINEAR	获取价格	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28352OC	CYPRESS	获取价格	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28352OC	SILICON	获取价格	PLL Based Clock Driver, 28352 Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30
CY28352OC-400	SILICON	获取价格	PLL Based Clock Driver, PDSO28, 5.3 MM, SOP-28

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