CY28352OCT

更新时间： 2024-02-13 23:33:18

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动器双倍数据速率时钟
页数	文件大小	规格书
8页	173K
描述
Differential Clock Buffer/Driver DDR400- and DDR333-Compliant

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CY28352OCT 数据手册

CY28352

Differential Clock Buffer/Driver DDR400-

and DDR333-Compliant

Description

Features

• Supports 333-MHz and 400-MHz DDR SDRAM

• 60- – 200-MHz operating frequency

This PLL clock buffer is designed for 2.5-V_DDand 2.5-AV_DD

operation and differential output levels.

This device is a zero delay buffer that distributes a clock input

CLKIN to six differential pairs of clock outputs (CLKT[0:5],

CLKC[0:5]) and one feedback clock output FBOUT. The clock

outputs are controlled by the input clock CLKIN and the

feedback clock FBIN.

• Phase-locked loop (PLL) clock distribution for double

data rate synchronous DRAM applications

• Distributes one clock input to six differential outputs

• External feedback pin FBIN is used to synchronize

output to clock input

The two-line serial bus can set each output clock pair

(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV_DDis

grounded, the PLL is turned off and bypassed for test

purposes.

• Conforms to DDRI specification

• Spread Aware™ for electromagnetic interference (EMI)

reduction

The PLL in this device uses the input clock CLKIN and the

feedback clock FBIN to provide high-performance, low-skew,

low–jitter output differential clocks.

• 28-pin SSOP package

Block Diagram

Pin Configuration

CLKC0

CLKT0

VDD

GND

CLKT0

CLKC0

CLKC5

CLKT5

CLKC4

CLKT4

VDD

CLKT1

CLKC1

CLKT1

CLKC1

GND

CLKT2

CLKC2

Serial

Interface

Logic

SCLK

SDATA

SCLK

CLKIN

SDATA

CLKT3

CLKC3

FBIN

FBOUT

AVDD

CLKT4

CLKC4

CLKIN

FBIN

AGND

VDD

PLL

CLKT3

CLKC3

GND

CLKT5

CLKC5

CLKT2

CLKC2

FBOUT

AVDD

28 pin SSOP

Cypress Semiconductor Corporation

Document #: 38-07371 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised Sept. 02, 2004

12 3 4 5 6 7 8

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