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CY28358OCT PDF预览

CY28358OCT

更新时间: 2024-02-22 22:56:17
品牌 Logo 应用领域
SPECTRALINEAR 驱动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
10页 136K
描述
200-MHz Differential Clock Buffer/Driver

CY28358OCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP28,.3
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.7
Is Samacsys:N输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:6
端子数量:28实输出次数:6
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5 V
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mm最小 fmax:200 MHz
Base Number Matches:1

CY28358OCT 数据手册

 浏览型号CY28358OCT的Datasheet PDF文件第2页浏览型号CY28358OCT的Datasheet PDF文件第3页浏览型号CY28358OCT的Datasheet PDF文件第4页浏览型号CY28358OCT的Datasheet PDF文件第5页浏览型号CY28358OCT的Datasheet PDF文件第6页浏览型号CY28358OCT的Datasheet PDF文件第7页 
CY28358  
200-MHz Differential Clock Buffer/Driver  
Description  
Features  
• Up to 200 MHz operation  
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD  
operation and differential output levels.  
• Phase-locked loop clock distribution for Double Data  
Rate Synchronous DRAM applications  
This device is a zero delay buffer that distributes a clock input  
CLKIN to six differential pairs of clock outputs (CLKT[0:5],  
CLKC[0:5]) and one feedback clock output FBOUT. The clock  
outputs are controlled by the input clock CLKIN and the  
feedback clock FBIN.  
• Distributes one clock input to six differential outputs  
• External feedback pin FBIN is used to synchronize the  
outputs to the clock input  
• Conforms to the DDR1 specification  
• Spread Aware™ for EMI reduction  
• 28-pin SSOP package  
The two line serial bus can set each output clock pair  
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is  
grounded, the PLL is turned off and bypassed for test  
purposes.  
The PLL in this device uses the input clock CLKIN and the  
feedback clock FBIN to provide high-performance, low-skew,  
low–jitter output differential clocks.  
Block Diagram  
Pin Configuration  
10  
CLKC0  
CLKT0  
VDD  
GND  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CLKT0  
CLKC0  
CLKC5  
CLKT5  
CLKC4  
CLKT4  
VDD  
2
3
CLKT1  
CLKC1  
CLKT1  
CLKC1  
GND  
4
5
CLKT2  
CLKC2  
Serial  
Interface  
Logic  
SCLK  
6
SDATA  
NC  
SCLK  
CLKIN  
NC  
7
SDATA  
CLKT3  
CLKC3  
8
FBIN  
9
FBOUT  
NC  
AVDD  
CLKT4  
CLKC4  
10  
11  
12  
13  
14  
CLKIN  
FBIN  
AGND  
VDD  
PLL  
CLKT3  
CLKC3  
GND  
CLKT5  
CLKC5  
CLKT2  
CLKC2  
FBOUT  
AVDD  
28 pin SSOP  
Rev 1.0, November 20, 2006  
Page 1 of 10  
www.SpectraLinear.com  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  

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