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CY28359OIT

更新时间: 2024-02-29 17:04:42
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
8页 186K
描述
273-MHz 6-Output Buffer for DDR400 DIMMS

CY28359OIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7系列:28359
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:10.2 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:6
端子数量:28实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:2 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

CY28359OIT 数据手册

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PRELIMINARY  
CY28359  
273-MHz 6-Output Buffer for DDR400 DIMMS  
Features  
Functional Description  
• Dual 1- to 3-output buffer/driver  
• Supports up to 2 DDR DIMMs  
• Outputs are individually enabled/disabled  
• Low-skew outputs (< 100 ps)  
• Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM  
• SMBus Read and Write support  
• Space-saving 28-pin SSOP package  
The CY28359 is a 2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 6 differ-  
ential outputs. Designers can configure these outputs to  
support up to two DDR DIMMs. The CY28359 can be used in  
conjunction with the CY28326 or similar clock synthesizer for  
the VIA P4X600 chipset.  
The CY28359 also includes an SMBus interface which can  
enable or disable each output clock. On power-up, all output  
clocks are enabled.  
Block Diagram  
Pin Configuration  
BUF_INA  
FB_OUTA  
DDRAT0  
DDRAC0  
DDRAT1  
DDRAC1  
DDRAT2  
DDRAC2  
DDRBT0  
DDRBC0  
DDRBT1  
DDRBC1  
DDRBT2  
DDRBC2  
FB_OUTB  
BUF_INB  
DDRBT0  
DDRBC0  
DDRBT1  
DDRBC1  
VDD  
VDD  
VSS  
SEL_ADDR  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
2
3
DDRBT2  
DDRBC2  
4
5
SDATA  
SEL_ADDR  
SCLK  
VSS  
6
SMBus  
Decoding  
VDD  
7
VSS  
FB_OUTA  
BUF_INA  
DDRAT2  
DDRAC2  
SDATA  
SCLK  
8
9
10  
11  
12  
13  
14  
VSS  
DDRAT0  
DDRAC0  
DDRAT1  
VSS  
BUFF_INB  
FB_OUTB  
VDD  
DDRAC1  
28 PIN SSOP  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07636 Rev. **  
Revised February 16, 2004  

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