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CY28372

更新时间: 2024-11-06 23:16:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
18页 284K
描述
SiS 746 AMD Athlon/AMD Duron Clock Synthesizer

CY28372 数据手册

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CY28372  
SiS 746 AMD Athlon™/AMD Duron™ Clock Synthesizer  
• One differential CPU clock (opendrain)  
• One singled-ended CPU clock (opendrain)  
• SMBus support with readback capabilities  
Features  
Supports AMD Athlon/DuronCPU  
• 3.3V and 2.5V power supply  
• Eight copies of PCI clocks  
• One 48-MHz USB clock  
• Spread Spectrum electromagnetic interference (EMI)  
reduction  
48-pin SSOP package  
• Two copies of ZCLK clocks  
• One 48-MHz/24-MHz programmable SIO clock  
CPU  
x 2  
ZCLK  
x 2  
REF  
x 3  
PCI  
x 8  
AGP  
x 2  
IOAPIC  
x 2  
48M  
x 1  
24_48M  
x 1  
Block Diagram  
Pin Configuration  
VDD_REF  
REF0:2  
XIN  
XOUT  
XTAL  
OSC  
VDD_REF  
**FS0/REF0  
**FS1/REF1  
REF2  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD_APIC  
IOAPIC1  
PLL Ref Freq  
2
VDD_CPU  
CPUT1  
3
IOAPIC0  
4
GND_APIC  
Divider  
PLL 1  
CPUT0, CPUC0  
Network  
5
GND_REF  
XIN  
CPU_STP#*  
CPUT1  
6
VDD_Z  
ZCLK0:1  
7
XOUT  
VDD_CPU  
GND_CPU  
CPUT0  
**FS0:3  
8
GND_Z  
ZCLK0  
CPU_STP#  
9
VDD_APIC  
APIC0:1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
ZCLK1  
CPUC0  
VDD_Z  
VDD_CPU  
GNDA  
*PCI_STP#  
VDD_PCI  
**FS2/PCIF0  
*FS3/PCIF1  
PCI0  
VDD_PCI  
PCIF0:1  
VDDA  
2
SCLK  
PCI0:5  
SDATA  
PCI_STP#  
PD#*  
VDD_AGP  
AGP0:1  
PCI1  
GND_AGP  
AGP0  
Fract.  
PLL2  
Aligner  
GND_PCI  
VDD_PCI  
PCI2  
AGP1  
VDD_AGP  
VDD_48  
48MHZ  
PCI3  
VDD_48  
48 MHz  
PCI4  
PD#  
PCI5  
24_48MHZ  
GND_48  
GND_PCI  
24_48MHz  
2
SDATA  
SCLK  
I2C  
Logic  
SSOP-48  
* : Internal Pull-up 150k  
** : Internal Pull-down 150k  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07533 Rev. *A  
Revised September 20, 2004  

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