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CY2545IXXXT PDF预览

CY2545IXXXT

更新时间: 2024-11-18 03:04:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
17页 336K
描述
Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface

CY2545IXXXT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:4 X 4 MM, LEAD FREE, MO-220, QFN-24
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm湿度敏感等级:3
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:166 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3 V主时钟/晶体标称频率:48 MHz
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Generators最大供电电压:2.75 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY2545IXXXT 数据手册

 浏览型号CY2545IXXXT的Datasheet PDF文件第2页浏览型号CY2545IXXXT的Datasheet PDF文件第3页浏览型号CY2545IXXXT的Datasheet PDF文件第4页浏览型号CY2545IXXXT的Datasheet PDF文件第5页浏览型号CY2545IXXXT的Datasheet PDF文件第6页浏览型号CY2545IXXXT的Datasheet PDF文件第7页 
CY2545  
CY2547  
PRELIMINARY  
Quad PLL Programmable Spread Spectrum  
2
Clock Generator with Serial I C Interface  
Features  
Benefits  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Four fully integrated phase locked loops (PLLs)  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Nonvolatile programming for personalization of PLL  
frequencies,spreadspectrumcharacteristics,drivestrength,  
crystal load capacitance, and output frequencies  
Wide operating output frequency range  
3 to 166 MHz  
Serial programmable over 2-wire I2C interface  
Application specific programmable EMI reduction using  
Spread Spectrum for clocks  
Programmable PLLs for system frequency margin tests  
Programmable Spread Spectrum with Center and Down  
Spread option and Lexmark and Linear modulation profiles  
Meets critical timing requirements in complex system  
designs  
VDD core voltage options:  
2.5V, 3.0V, and 3.3V for CY2545  
1.8V for CY2547  
Suitability for PC, consumer, portable, and networking appli-  
cations  
Capable of Zero PPM frequency synthesis error  
Selectable output clock voltages:  
2.5V, 3.0V, and 3.3V for CY2545  
1.8V for CY2547  
Uninterrupted system operation during clock frequency  
switch  
Application compatibility in standard and low power systems  
Power down, output enable, or frequency select features  
Low jitter, high accuracy outputs  
Ability to synthesize nonstandard frequencies with  
Fractional-N capability  
Up to eight clock outputs with Programmable drive strength  
Glitch-free outputs while frequency switching  
24-pin QFN package  
Commercial and Industrial temperature ranges  
Logic Block Diagram  
CLKIN/RST  
4 of 6  
Crossbar  
Switch  
CLK1  
CLK2  
XIN/  
EXCLKIN  
Bank  
1
Output  
OSC  
PLL1  
XOUT  
Dividers  
and  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
Bank  
2
Drive  
PLL2  
Strength  
Control  
MUX  
and  
Control  
Logic  
FS  
Bank  
3
PLL3  
(SS)  
CLK  
8
SCL  
SDA  
PLL4  
(SS)  
I2C  
PD#/OE  
SSON  
Cypress Semiconductor Corporation  
Document #: 001-13196 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 29, 2007  
[+] Feedback  

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