Datasheet > CY241V08-41

CY241V08-41

更新时间： 2022-01-19 01:08:00

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
6页	45K
描述
Clocks and Buffers

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中文翻译

获取价格

数据手册

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CY241V08-41 数据手册

PRELIMINARY

CY241V08-41

Data Retention @ Tj = 125°C................................> 10 years

Package Power Dissipation...................................... 350 mW

ESD (Human Body Model) MIL-STD-883.................> 2000V

Absolute Maximum Conditions

Supply Voltage (V_DD) ........................................–0.5 to +7.0V

DC Input Voltage...................................... –0.5V to V_DD+ 0.5

Storage Temperature (Non-condensing).....–55°C to +125°C

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Junction Temperature ................................ –40°C to +125°C

Pullable Crystal Specifications^[1]

Parameter

Description

Comments

Min. Typ. Max. Unit

F_NOM

Nominal crystal frequency

Parallel resonance, fundamental mode, AT

cut

–

MHz

C_LNOM

R₁

Nominal load capacitance

–

Ω

–

Equivalent series resistance (ESR)

Fundamental mode

R₃/R₁

Ratio of third overtone mode ESR to

fundamental mode ESR

Ratio used because typical R₁values are

much less than the maximum spec

–

Crystal drive level

No external series resistor assumed

–

400

–

150

–

µW

F_3SEPHI

F_3SEPLO

C₀

Third overtone separation from 3*F_NOMHigh side

Third overtone separation from 3*F_NOMLow side

Crystal shunt capacitance

ppm

–200 ppm

–

C₀/C₁

C₁

Ratio of shunt to motional capacitance

Crystal motional capacitance

180

250

21.6

14.4 18

Recommended Operating Conditions

Parameter

Description

Min.

3.135

Typ.

3.3

–

Max.

Unit

V_DD

T_A

Operating Voltage

3.465

Ambient Temperature

°C

C_LOAD

t_PU

Max. Load Capacitance

–

Power-uptimefor allV_DDpinstoreachminimumspecified

voltage (power ramps must be monotonic)

0.05

–

500

DC Electrical Specifications

Parameter

I_OH

Name

Description

V_OH= V_DD– 0.5V, V_DD= 3.3V

V_OL= 0.5V, V_DD= 3.3V

Except XIN, XOUT pins

Min.

–

Typ.

Max.

Unit

Output HIGH Current

Output LOW Current

Input Capacitance

VCXO Input Range

VCXO Pullability Range

Supply Current

–

I_OL

C_IN

V_VCXO

f_∆XO

I_VDD

–

V_DD

±150

–

ppm

–

AC Electrical Specifications (V_DD= 3.3V)^[1]

Parameter^[1]

Name

Output Duty Cycle

Rising Edge Rate

Description

Min.

Typ. Max. Unit

Duty Cycle is defined in Figure 1, 50% of V_DD

–

Output Clock Edge Rate, Measured from 20%

0.8

1.4

V/ns

to 80% of V_DD, C_LOAD= 15 pF. See Figure 2.

Falling Edge Rate

Output Clock Edge Rate, Measured from 80%

0.8

1.4

–

V/ns

to 20% of V_DD, C_LOAD= 15 pF. See Figure 2.

t₉

Clock Jitter 83.33 MHz

Clock Jitter XBUF/27 MHz

PLL Lock Time

Peak-to-peak period jitter

–

500

375

t₁₀

Note:

1. Not 100% tested.

Document #: 38-07570 Rev. **

Page 3 of 6

1 234 5 6

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