Datasheet > CY23S05SXI-1

CY23S05SXI-1

更新时间： 2024-09-17 14:56:11

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
13页	270K
描述
Low Cost 3.3V Spread Aware Zero Delay Buffer

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数据手册

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CY23S05SXI-1 数据手册

CY23S09, CY23S05

Low Cost 3.3 V Spread Aware

Zero Delay Buffer

All parts have on-chip PLLs that lock to an input clock on the REF

pin. The PLL feedback is on-chip and is obtained from the

CLKOUT pad.

Features

■ 10 MHz to 100 MHz and 133 MHz operating range, compatible

with CPU and PCI bus frequencies

The CY23S09 has two bans of four outputs each, which can be

controlled by the select inputs as shown in the Select Input

Decoding table on Select Input Decoding for CY23S09 on page

4. If all output clocks are not required, Bank B can be

three-stated. The select inputs also allow the input clock to be

directly applied to the outputs for chip and system testing

purposes.

■ Zero input-output propagation delay

■ Multiple low skew outputs

❐ Output-output skew less than 250 ps

❐ Device-device skew less than 700 ps

❐ One input drives five outputs (CY23S05)

❐ One input drives nine outputs, grouped as 4 + 4 + 1

The CY23S09 and CY23S05 PLLs enter a power down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 A of current draw (for commercial temperature

devices) and 25.0 A (for industrial temperature devices). The

CY23S09 PLL shuts down in one additional case, as shown in

the Select Input Decoding for CY23S09 on page 4.

(CY23S09)

■ Less than 200 ps Cycle-to-cycle jitter

■ Test mode to bypass PLL (CY23S09 only, see Select Input

Decoding for CY23S09 on page 4)

■ Available in space saving 16-pin, 150-mil SOIC, 4.4 mm

TSSOP (CY23S09) or 8-pin, 150-mil

SOIC package (CY23S05)

Multiple CY23S09 and CY23S05 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

■ 3.3 V operation, advanced 0.65 CMOS technology

■ Spread Aware

All outputs have less than 200 ps of cycle-to-cycle jitter. The input

to output propagation delay on both devices is guaranteed to be

less than 350 ps; the output to output skew is guaranteed to be

less than 250 ps.

Functional Description

The CY23S05 and CY23S09 is available in two different config-

urations, as shown in the Ordering Information on page 8. The

CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H

and CY23S09-1H is the high drive version of the -1, and its rise

and fall times are much faster than -1.

The CY23S09 is a low cost 3.3 V zero delay buffer designed to

distribute high speed clocks and is available in a 16-pin SOIC

package. The CY23S05 is an 8-pin version of the CY23S09. It

accepts one reference input, and drives out five low skew clocks.

The -1H versions of each device operate at up to 100 and

133 MHz frequencies and have higher drive than the -1 devices.

For a complete list of related resources, click here.

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 38-07296 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 07, 2014

12 3 4 5 6 7...13

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与CY23S05SXI-1相关器件

型号	品牌	获取价格	描述	数据表
CY23S05SXI-1T	INFINEON	获取价格	Low Cost 3.3V Spread Aware Zero Delay Buffer
CY23S08	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08_07	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08_08	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08_09	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-1HT	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-1T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-2	CYPRESS	获取价格	3.3V Zero Delay Buffer

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