CY23S08SC-1T

更新时间： 2024-09-15 22:25:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
8页	167K
描述
3.3V Zero Delay Buffer

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技术参数
数据手册

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CY23S08SC-1T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.7	系列：	23S
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	9.893 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.008 A
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	8
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
Prop。Delay @ Nom-Sup：	0.275 ns	传播延迟（tpd）：	0.35 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.3 ns
座面最大高度：	1.727 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm
最小 fmax：	140 MHz	Base Number Matches：	1

CY23S08SC-1T 数据手册

PRELIMINARY

CY23S08

3.3V Zero Delay Buffer

The CY23S08 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in Table 1. If all

output clocks are not required, Bank B can be three-stated.

The select inputs also allow the input clock to be directly

applied to the output for chip and system testing purposes.

The CY23S08 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases as shown in Table 1.

Multiple CY23S08 devices can accept the same input clock

and distribute it in a system. In this case, the skew between

the outputs of two devices is guaranteed to be less than

700 ps.

The CY23S08 is available in five different configurations, as

shown in Table 2. The CY23S08–1 is the base part, where the

output frequencies equal the reference if there is no counter in

the feedback path. The CY23S08–1H is the high-drive version

of the –1, and rise and fall times on this device are much faster.

Features

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations, see Table 2

• Multiple low-skew outputs

— Output-output skew less than 200 ps

— Device-device skew less than 700 ps

— Two banks of four outputs, three-stateable by two

select inputs

• 10-MHz to 133-MHz operating range

• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4)

• Advanced 0.65µ CMOS technology

• Space-saving 16-pin 150-mil SOIC/TSSOP packages

• 3.3V operation

• Spread Aware™

The CY23S08–2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin. The CY23S08–2H is the high-drive version of

the –2, and rise and fall times on this device are much faster.

Functional Description

The CY23S08 is a 3.3V zero delay buffer designed to

distribute high-speed clocks in PC, workstation, datacom,

telecom, and other high-performance applications.

The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be

driven into the FBK pin, and can be obtained from one of the

outputs. The input-to-output propagation delay is guaranteed

to be less than 350 ps, and output-to-output skew is

guaranteed to be less than 250 ps.

The CY23S08–3 allows the user to obtain 4X and 2X

frequencies on the outputs.

The CY23S08–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile, and can be used

in a variety of applications.

Pin Configuration

Block Diagram

FBK

PLL

SOIC

REF

MUX

Top View

CLKA1

REF

CLKA1

FBK

CLKA2

CLKA3

CLKA4

Extra Divider (–3, –4)

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

Select Input

CLKB4

CLKB3

Decoding

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –2H, –3)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07265 Rev. *D

Revised June 03, 2004

12 3 4 5 6 7 8

中文翻译

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与CY23S08SC-1T相关器件

型号	品牌	获取价格	描述	数据表
CY23S08SC-2	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-2H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-2HT	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-2T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-3	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-3T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-4	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SC-4T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SI-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY23S08SI-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer

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