CY2305
CY2309
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Input LOW Voltage[5]
Test Conditions
Min
–
Max
0.8
Unit
V
VIL
VIH
IIL
Input HIGH Voltage[5]
Input LOW Current
Input HIGH Current
Output LOW Voltage[6]
2.0
–
–
V
VIN = 0V
50.0
100.0
0.4
μA
μA
V
IIH
VIN = VDD
–
VOL
IOL = 8 mA (–1)
IOH =12 mA (–1H)
–
Output HIGH Voltage[6]
VOH
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
I
DD (PD mode)
Power down Supply Current
Supply Current
REF = 0 MHz
–
–
25.0
35.0
μA
IDD
Unloaded outputs at 66.67
MHz, SEL inputs at VDD
mA
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices[7]
Parameter
Name
Test Conditions
Min
Typ.
Max
Unit
MHz
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33 MHz
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
50.0
–
60.0
2.50
2.50
250
%
ns
ns
ps
ps
t3
t4
–
–
–
–
–
Output to Output Skew[6]
t5
85
–
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
±350
t6B
t7
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
–
5
–
8.7
ns
ps
CLKOUT Rising Edge[6]
Device to Device Skew[6]
Bypass Mode, CY2309 device only.
Measured at VDD/2 on the CLKOUT pins
of devices
700
Cycle to Cycle Jitter[6]
PLL Lock Time[6]
tJ
Measured at 66.67 MHz, loaded outputs
–
–
70
–
200
1.0
ps
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature
Devices[7]
Parameter
Name
Description
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33 MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Output to Output Skew[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
–
50.0
50.0
–
60.0
55.0
1.50
1.50
250
%
%
t3
ns
ns
ps
ps
t4
–
–
t5
–
85
–
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
±350
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
5
8.7
ns
CLKOUT Rising Edge[6]
Bypass Mode, CY2309 device only.
Document #: 38-07140 Rev. *H
Page 7 of 17
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