Datasheet > CY2309ESXI-1HT

CY2309ESXI-1HT

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
17页	383K
描述
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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CY2309ESXI-1HT 数据手册

CY2305

CY2309

Absolute Maximum Conditions

Supply Voltage to Ground Potential................–0.5V to +7.0V

DC Input Voltage (Except REF) ............–0.5V to V_DD+ 0.5V

DC Input Voltage REF .........................................–0.5V to 7V

Storage Temperature ................................. –65°C to +150°C

Junction Temperature................................................. 150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ...........................> 2,000V

Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter

V_DD

Description

Min

3.0

Max

3.6

Unit

Supply Voltage

T_A

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

°C

C_L

C_IN

t_PU

–

Power up time for all V_DDs to reach minimum specified voltage

(power ramps must be monotonic)

0.05

Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature

Devices

Parameter

V_IL

Description

Input LOW Voltage^[5]

Input HIGH Voltage^[5]

Input LOW Current

Input HIGH Current

Output LOW Voltage^[6]

Test Conditions

Min

–

Max

0.8

Unit

V_IH

I_IL

2.0

–

V_IN= 0V

50.0

100.0

0.4

μA

I_IH

V_IN= V_DD

–

V_OL

I_OL= 8 mA (–1)

–

_{OH =}12 mA (–1H)

I_OH= –8 mA (–1)

_OL= –12 mA (–1H)

Output HIGH Voltage^[6]

V_OH

2.4

–

I_DD(PD mode) Power Down Supply Current REF = 0 MHz

–

12.0

32.0

μA

I_DD

Supply Current

Unloaded outputs at 66.67 MHz,

SEL inputs at V_DD

Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature

Devices ^[7]

Parameter

Name

Test Conditions

Min

Typ.

Max

Unit

Output Frequency

30-pF load

10 pF load

–

100

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Measured at 1.4V, F_out= 66.67

MHz

40.0

50.0

–

60.0

2.50

t₄

t₅

Measured between 0.8V and

2.0V

–

Fall Time^[6]

Measured between 0.8V and

2.0V

–

Output to Output Skew^[6]

All outputs equally loaded

Measured at V_DD/2

–

250

t_6A

Delay, REF Rising Edge to

CLKOUT Rising Edge^[6]

±350

Notes

5. REF input has a threshold voltage of V /2.

6. Parameter is guaranteed by design and characterization. Not 100% tested in production.

7. All parameters specified with loaded outputs.

Document #: 38-07140 Rev. *H

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