Datasheet > CY2309NZSXI-1HT

CY2309NZSXI-1HT

更新时间： 2023-12-06 20:12:11

品牌	Logo	应用领域
英飞凌 - INFINEON		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
11页	1048K
描述
3.3V Non Zero Delay Buffer

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数据手册

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CY2309NZSXI-1HT 数据手册

CY2309NZ

Nine-Output 3.3 V Buffer

Nine-Output 3.3

V Buffer

Features

Functional Description

■ One-input to nine-output buffer/driver

The CY2309NZ is a low-cost buffer designed to distribute

high-speed clocks in mobile PC systems and desktop PC

systems with SDRAM support. The part has nine outputs, eight

of which can be used to drive two DIMMs or four SO-DIMMs, and

the remaining can be used for external feedback to a PLL. The

device operates at 3.3 V and outputs can run up to 133.33 MHz.

■ Supports two DIMMs or four SO-DIMMs with one additional

output for feedback to an external or chipset phase-locked loop

(PLL)

■ Low power consumption for mobile applications

❐ Less than 32 mA at 66.6 MHz with unloaded outputs

The CY2309NZ is designed for low EMI and power optimization.

It has multiple V_SSand V_DDpins for noise optimization and

consumes less than 32 mA at 66.6 MHz, making it ideal for the

low-power requirements of mobile systems. It is available in an

ultra-compact 150-mil 16-pin SOIC package.

■ 1-ns input-output delay

■ Buffers all frequencies from 2 MHz to 133.33 MHz

■ Output-output skew less than 250 ps

For a complete list of related documentation, click here.

■ Multiple V_DDand V_SSpins for noise and electromagnetic

interference (EMI) reduction

■ Space-saving 16-pin 150-mil small-outline integrated circuit

(SOIC) package

■ 3.3-V operation

■ Industrial temperature available

Logic Block Diagram

BUF_IN

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

OUTPUT5

OUTPUT6

OUTPUT7

OUTPUT8

OUTPUT9

Cypress Semiconductor Corporation

Document Number: 38-07182 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 14, 2016

12 3 4 5 6 7...11

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